ECS Interface Library User Guide
1MHz version
Version: Release_v1.5
Created: 25/02/2006
Last modified: 19.06.2006
Prepared by: Hui Gong, Alex Gong, Hou Lei and Guido Haefeli
Note that this document is strongly related to the TELL1 firmware version!
Document status sheet
Revision / Date / Reason for change1.5 / 29.6.2006 / Separate the ECS vhdl manual from the register and memory map,
Update the ecs implementation to the current version! The ecs_reg register array is not available anymore in the components and registers.
1.4 / 7.4.2006 / Change the position of the IP destination bits to be split over the last two bytes of the address (6 and 6)
Remove MAC dest register in simu reg and add the two last bit of L0-EvCnt
Add max cluster reg
Add header correction register (en, strip0 and 1)
Change that the destination MAC address does not change
Use one complete byte in the source MAC address to encode the port that is used to sent of the data
Add interrupt bit
Add external trigger input
Add max cluster cut register
1.3 / 6.4.2006 / Add trigger fifo used word monitor regs
Add fem_dv_count monitor reg
Add Reorder ram and reg for Velo
Add r,phi reorder bit for Velo in PP_CTRL_REG0
1.2 / 02/03/2006 / Remove definition for L1T in GBE port select
Added bank class register
1.1 / 25/02/2006 / Add Testpulse delay register SyncLink 0x30
Add MTU size register SyncLink 0x34
1.0 / 15/02/2006 / First version for the 1MHz readout
1. Two Parts of Memories 7
2. Significant Signal Description 7
3. ECS Memory Map 7
3.1 Common ECS Memory Map 7
3.1.1 GBE memory map 8
3.2 Internal Memory Map 9
3.3 External Memory Map (not used anymore for the TELL1 without L1Buffer as it is for LHCb in the 1MHz readout mode) 11
4. Detailed Description of Internal Memory Map 12
5. How to add an User Specific Register 13
1) Define 5 constants in “user_tell1_lib. user_TELL1_type_map” 13
2) Add the register component: ecs_register 14
6. How to add an User Specific RAM, ROM and FIFO 16
6.1 How to add an User Specific RAM block 16
1) Define 4 constants in pp_fpga_user_memory_map 16
2) Add the RAM component: xxx_ram 17
3) Add the RAM multiplexer component: ecs_ram_mux 17
4) Connect xxx_ram block with ecs_ram_mux component 19
6.2 How to add an User Specific ROM block 19
1) Define 4 constants in pp_fpga_user_memory_map 19
2) Add the ROM component: xxx_rom 19
6.3 How to add an User Specific FIFO block 20
1) Define 3 constants 20
2) Add the FIFO component: xxx_fifo 20
3) Add the FIFO multiplexer component: ecs_fifo_mux 21
4) Connect xxx_fifo block with ecs_fifo_mux component 23
7. Registers and RAM blocks Definition of PP-FPGA 24
7.1 Common Registers 24
PP_RESET_REG ($0x000000) 24
PP_CTRL_REG0 ($0x000004) 24
PP_CTRL_REG1 ($0x000008) 25
CONSTANT_REG ($0x001000) 25
EVT_ASSEM_CNT_REG ($0x001004) 25
PP_TRIGGER_CNT_REG ($0x001008) 26
PP_BANK_CNT_REG0 ($0x00100C) 26
PP_BANK_CNT_REG1 ($0x001010) 26
PP_EVENT_CNT_REG ($0x001014) 26
BER_ERROR_CNT_REG ($0x001018) 26
BER_RCV_CNT_H_REG ($0x00101C) 27
BER_ RCV_CNT_L _REG ($0x001020) 27
MEM_MAX_USAGE_REG0 ($0x001024) 27
MEM_MAX_USAGE_REG1 ($0x001028) 27
PP_ECS_ERROR_CNT_REG ($0x00102C) 27
PP_DERAND_EVNT_CNT_REG ($0x001030) 27
PP_DATE_REG ($0x001034) 28
PP_TIME_REG ($0x001038) 28
PP_VERSION_REG ($0x00103C) 28
7.2 User Specific Register 28
7.2.1 VELO specific registers (starts from 0x002000) 28
VELO_ADCCLK_PHY_DLY_REGH ($0x002000) 28
VELO_ADCCLK_PHY_DLY_REGL ($0x002004) 29
VELO_ADCCLK_CYC_DLY_REG ($0x002008) 29
9 CLUS_PARA_REG ($0x00200C, $0x002010 …$0x00202C) 29
ADC_LINK_PROBE_REG ($0x002030) 30
ADC_LINK_SYNC_REG ($0x002034) 30
VELO_PHI_REORDER_STRIP_CNT_REG ($0x002038) 31
VELO_HEADER_CORRECTION_VALUE_STRIP_O_REG ($0x00203C) 31
VELO_HEADER_CORRECTION_VALUE_STRIP_1_REG ($0x002040) 31
VELO_CLUSTER_NUMBER_MAX_REG ($0x002044) 31
7.2.2 ST specific registers (starts from 0x003000) 31
ORX_CTRL REG ($0x003000) 31
12 CLUS_PARA_REG ($0x003004, $0x003008 …$0x003030) 32
OPT_BEETLE_PROBE_REG ($0x003034) 33
OPT_BEETLE_SYNC_REG ($0x003038) 33
ST_HEADER_CORRECTION_VALUE_STRIP_O_REG ($0x00303C) 34
ST_HEADER_CORRECTION_VALUE_STRIP_1_REG ($0x003040) 34
ST_CLUSTER_NUMBER_MAX_REG ($0x003044) 34
7.2.3 OT specific registers (starts from 0x000480) 34
7.2.4 CAL specific registers (starts from 0x0004C0) 34
7.2.5 MUON specific registers (starts from 0x000500) 34
7.3 Common RAM blocks 35
DATA_GEN_RAM SectionA (Address range: 0x100000 – 0x1001FF) 35
DATA_GEN_RAM SectionB (Address range: 0x102000 – 0x1021FF) 35
DATA_GEN_RAM SectionC (Address range: 0x104000 – 0x1041FF) 35
DATA_GEN_RAM SectionD (Address range: 0x106000 – 0x1061FF) 35
DATA_GEN_RAM SectionE (Address range: 0x108000 – 0x1081FF) 36
DATA_GEN_RAM SectionF (Address range: 0x10A000 – 0x10A1FF) 36
7.4 User Specific RAM blocks 36
7.2.3 VELO specific RAM (starts from 0x200000) 36
8 PEDESTAL RAM (Address range: 0x200000 – 0x2000FF, 0x202000-0x2020FF,….,, 0x20E000 - 0x20E0FF) 36
9 HIT_THRESHOLD RAM (Address range: 0x210000–0x2100FF, 0x212000-0x2120FF, … , 0x220000-0x2200FF) 37
9 CMS_THRESHOLD RAM (Address range: 0x222000–0x2220FF, 0x224000-0x2240FF, … , 0x232000-0x2320FF) 37
1 VELO_AVERAGE_HISTOGRAM (Address range: 0x234000–0x237FFF) 37
--ram26 37
1 VELO_SLOPE_HISTOGRAM (Address range: 0x238000–0x23BFFF) 37
--ram28 38
3 VELO_REORDER_RAM (Address range: 0x23C000–0x23C0FF, 0x23E000–0x23E0FF, 0x240000–0x2400FF) reserve 38
7.2.4 ST specific RAM (starts from 0x300000) 38
12 PEDESTAL RAM (Address range: 0x300000 – 0x3000FF, 0x302000-0x3020FF,….,, 0x316000 - 0x3160FF) 38
12 HIT_THRESHOLD RAM (Address range: 0x318000 – 0x3180FF, 0x31A000-0x31A0FF,….,, 0x32E000 - 0x32E0FF) 38
12 CMS_THRESHOLD RAM (Address range: 0x330000 – 0x3300FF, 0x332000-0x3320FF,….,, 0x346000 - 0x3460FF) 39
1 ST_AVERAGE_HISTOGRAM (Address range: 0x348000– 0x349800) 39
--ram36 39
1 ST_SLOPE_HISTOGRAM (Address range: 0x34C000–0x34D800) 39
--ram38 39
7.4.3 OT specific RAM (starts from 0x400000) 39
7.4.4 CAL specific RAM (starts from 0x500000) 39
7.4.5 MUON specific RAM (starts from 0x600000) 39
8. Registers and RAM blocks Definition of SyncLink-FPGA 39
8.1 Common Registers 39
SL_RESET_REG ($0x000000) 39
SL_CTRL_REG0 ($0x000004) 40
SL_CTRL_REG1 ($0x000008) 41
SL_SIMU_CTRL_REG ($0x00000C) 42
SPI3_TX_CTRL_REG ($0x000010) 42
SPI3_RX_CTRL_REG ($0x000014) 43
THRO_CTRL_REG ($0x000018) 43
THRO_CNT_REG ($0x00001C) 43
MEP_PID_REG ($0x000020) 44
ECS_SIMU_TRIG_NUM_REG ($0x000024) 44
ECS_SIMU_TRIG_SCHE_REG ($0x000028) 44
SEP_MSB4_REG ($0x00002C) 44
PEDESTAL_BANK_SCHEDULE_CTRL_REG ($0x000030) 45
BANK_HEADER2_REG ($0x000034) 45
SL_TP_REG ($0x000038) 45
MTU_SIZE_REG ($0x00003C) 46
BANK_CLASS_REG ($0x000040) 46
SL_PP_PROB_REG ($0x001000) 46
SL_EVT_IN_CNT_REG ($0x001004) 47
SL_EVT_OUT_CNT_REG ($0x001008) 47
SPI3_TX_MEP_CNT_REG ($0x001010) 47
SPI3_TX_WORD_CNT_REG ($0x001014) 47
SPI3_TX_SOP_CNT_REG ($0x001018) 47
SPI3_TX_EOP_CNT_REG ($0x00101C) 47
TTC_TRIG_CNT_REG ($0x001020) 47
TTC_TRIG_TYPE_CNT_REG ($0x001024) 48
TTC_DEST_IP_CNT_REG ($0x001028) 48
TTC_RESET_SIG_CNT_REG ($0x00102C) 48
SL_TRIG_CNT_REG ($0x001030) 48
TRIG_INFO_TX_CNT_REG ($0x001034) 48
TRIG_INFO_REQ_CNT_REG ($0x001038) 48
TRIG_INFO_FIFO_MON_REG0 ($0x00103C) 48
TRIG_INFO_FIFO_MON_REG1 ($0x001040) 49
MEP_WRITE_CNT_REG ($0x001044) 49
MEP_READ_CNT_REG ($0x001048) 50
MEP_MAX_USAGE_REG ($0x00104C) 50
SL_ECS_ERROR_CNT_REG ($0x001050) 50
SL_MAX_USE_REG ($0x001054) 50
FROZEN_EVID_REG ($0x001058) 50
FROZEN_BCNT_REG ($0x00105C) 50
FRAMER_MAX_USE_REG ($0x001060) 51
REAL_RATE_REG0 ($0x001064) 51
REAL_RATE_REG1 ($0x001068) 51
REAL_RATE_REG2 ($0x00106C) 51
REAL_RATE_REG3 ($0x001070) 51
REAL_RATE_REG4 ($0x001074) 51
SL_FLOWCTRL_MONITOR_REG ($0x001078) 52
MEP_GT_16K_CNT_REG ($0x00107C) 52
SL_DATE_REG ($0x001080) 52
SL_TIME_REG ($0x001084) 53
SL_VERSION_REG ($0x001088) 53
SL_TRIGGER_FIFO_USED_REG0 ($0x00108C) 53
SL_TRIGGER_FIFO_USED_REG1 ($0x001090) 53
SL_FEM_DV_CNT_REG ($0x001094) 53
SL_DEST_IP_L0_EVID_LSB_ERROR_CNT_REG ($0x001098) 53
8.3 Common RAM blocks 54
MEP_LOCATION_RAM (Address range: 0x100000 – 0x1001FF) 54
IPv4_HEADER_RAM (Address range: 0x102000 - 0x10207F) 54
INTEL_MAC_LPB_TX_RAM (Address range: 0x104000 - 0x1043FF) 56
INTEL_MAC_LPB_RX_RAM (Address range: 0x106000 – 0x1063FF) 57
SEP_GEN_RAM (Address range: 0x200000 – 0x20FFFF) 57
8.4 User Specific RAM blocks 57
9. I2C bus address definition 57
I2C BUS 0 (mixed) 57
I2C BUS 1 (FPGA bus) 58
I2C BUS 2 (A-Rx DAC bus) 58
I2C BUS 3 (GBE Tx card bus) 59
Appendix: Example codes for C access 59
1. Two Parts of Memories
The memories employed by Tell1 DAQ are separated into two parts: Internal Memory and External Memory.
Internal memory includes Registers, FIFO, RAM and ROM on the FPGA chip.
External memory includes L1 DDR SDRAM for PP-FPGA and QDR SRAM for SyncLink-FPGA.
2. Significant Signal Description
1) ECSAD:
ECSAD is multiplexed for data and address of parallel local bus. Acting as data, it is 32-bit width. Acting as address, it is 28-bit width.
2) ChipAddr
3 hardwired pins on motherboard, to distinguish different FPGA. Refer to following table:
PP0 / PP1 / PP3 / PP4 / SyncLinkChipAddr / X”0” / X”1” / X”2” / X”3” / X”4”
3) Swap_page
Set in an 8-bit register in SyncLink FPGA and distributed to the PP FPGA.
3. ECS Memory Map
There are two kinds of ECS address. One kind is Common ECS Access Address. The other kind is Internal Memory ECS Address and External Memory ECS Address. And they are different. Among them, Common ECS Access Address must be set correctly by user when accessing a certain internal or external memory. However Internal Memory ECS Address and External Memory ECS Address don’t need to be set by user, they will be automatically calculated from Common ECS Access Address by ECS slave in each FPGA and distributed to internal and external memories. Although it is not necessary for user to set internal or External Memory ECS Address, it is still important for user to know internal and external memory map because we can’t set Common ECS address correctly if we don’t know internal and external memory map. These 3 memory maps will be illustrated in the following.
3.1 Common ECS Memory Map
Figure 3.1 Common ECS Memory Map
Common ECS Memory Map is as Figure 3.1. In fact, Common ECS Access Address composes of two parts: 28-bit ECSAD and 8-bit swap_page. The 28-bit ECSAD is generated by parallel local bus. And 8-bit swap page can be set in SyncLink FPGA and will be distributed to 4 PP FPGA. Swap_page is used to expand the memory space and merely used to access external memory because 28-bit ECSAD is adequate for accessing all the internal memory. The base address for GBE card is from 0x10000.
3.1.1 GBE memory map
To clarify what the memory space for the GBE looks like we give the read function used to access the GBE MAC registers. Note that the data bus for the MAC is only 16-bit wide. The 16-LSBs of the registers are mapped at the memory space to one region and the 16-MSBs to an other. The two regions have an offset of 0x800*4 in address range. Below we give the first part of the address definition used in the gbe library.
// the base address of for the 16-LSBs
#define INTEL_MAC_CH_BASE 0x00004000 * 4
// the offset for the 16-MSBs
#define INTEL_HIGH 0x00000800 * 4
#define INTEL_CH0_BASE 0x00004000 * 4
#define INTEL_CH1_BASE 0x00004080 * 4
#define INTEL_CH2_BASE 0x00004100 * 4
#define INTEL_CH3_BASE 0x00004180 * 4
#define INTEL_MAC_CH_OFFSET 0x00000080 * 4
/*-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-*/
int _intel_GBE_read(u_int32_t address, u_int32_t *value) //
/*-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-*/
{
int err =0;
u_int32_t rval;
u_int16_t hrval;
/* read low word */
err |= lb_read_hword(address, &hrval);
rval = hrval;
*value = 0x0000FFFF & rval; /* mask out upper side of bus */
/* read high word */
err |= lb_read_hword(address+INTEL_HIGH, &hrval);
rval = hrval;
*value = *value + ((0x0000FFFF & rval)<16); /* mask out, shift and add */
smart_return(err);
}
3.2 Internal Memory Map
Figure 3.2 Internal Memory Map for the PP_FPGA
At the moment, Internal Memory Map is like Figure 3.2 and the same for PP FPGA and SyncLink FPGA. From this figure, we know 24-bit Internal Memory ECS Address is used to access internal memory. As it was said, 24-bit Internal Memory ECS Address will be automatically calculated by ECS slave from Common ECS Access Address. The calculation algorithm is:
Internal_Memory_ECS_Address = ECSAD(23 .. 0)
The condition that Internal Memory ECS Address is valid is:
ChipAddr = "100" and ECSAD(27 downto 24) = "0001" --to access SyncLink FPGA
ECSAD(27) = 0 --to access internal memory
ChipAddr = "000" and ECSAD(27 downto 24) = "0100" --to access PP0 FPGA
ChipAddr = "001" and ECSAD(27 downto 24) = "0101" --to access PP1 FPGA
ChipAddr = "010" and ECSAD(27 downto 24) = "0110" --to access PP2 FPGA
ChipAddr = "011" and ECSAD (27 downto 24) = "0111" --to access PP3 FPGA
“ECSAD(27) = 0” indicates Common ECS Access Address is to access internal memory of the FPGA whose ChipAddr is corresponding with current ECSAD(26..24). Swap_page is not used for accessing internal memory because ECSAD(27.. 0) is enough for accessing all the internal memories on the 5 FPGA.
According the algorithm above, ECS slave can calculate the Internal Memory ECS Address. On the contrary, user can set the Common ECS Access Address correctly according to the algorithm above when accessing a certain internal memory.
Internal memory map will be detailed illustrated in Chapter 4.
3.3 External Memory Map (not used anymore for the TELL1 without L1Buffer as it is for LHCb in the 1MHz readout mode)
Figure 3.3 External Memory Map
From Figure 3.3, we know that 32-bit External Memory ECS Address is used to access External Memory, so the total memory space is 4 GB for each FPGA.
However, only the lowest 27 bits are used by PP FPGA to access its external memory: L1 DDR SDRAM. So the actual external memory space of PP FPGA is 128M bytes (no more than 1 swap page). For SyncLink FPGA, only the lowest 20 bits are used to access its external memory: QDR SRAM. The actual external memory space used by SyncLink FPGA is 1M bytes (less than 1 swap page).
Although the memory space used by PP FPGA is different from SyncLink FPGA, the algorithm that ECS slave calculates 32-bit External Memory ECS Address from Common ECS Access Address obviously is identical:
External_Memory_ECS_Address = swap_page(4 .. 0) & ECSAD(26 .. 0)
The condition that External Memory ECS Address is valid is:
ECSAD (27) = 1 --to access external memory
swap_page(7 .. 5) = ChipAddr
“ECSAD(27) = 1” indicates Common ECS Access Address is to access external memory of the FPGA whose ChipAddr is the same as swap_page(7 .. 5).
Since ECS slave can calculate the External Memory ECS Address according to the algorithm above, on the contrary, user can set the Common ECS Access Address correctly according to the algorithm above when accessing the external memory.
Because swap_page is used to access external memory, it is important to set the swap_page in the SWAP_PAGE_REG before accessing external memory!
Since the External Memory space of all FPGA is no more than 1 swap page, swap_page(4 .. 0 )should always be set to 0. About swap_page(7 .. 5 ), it obviously should be equal to the ChipAddr of the FPGA that need to be accessed.
In addition, ECSAD(27) should be set to 1 and ECSAD(26..0) should be set to the external memory address that needs to be accessed. About the detailed definition of ECSAD(26..0), there is a little difference between accessing L1b of PP FPGA and QDR of SyncLink FPGA by ECS.
When accessing L1b by ECS:
With DDR core, the data bus of L1b is 96-bit width, while the address bus of L1b is 23-bit width (2²³×96 is exactly equal to 3×256M bits: 3 SDRAM). Since it is 3 times of ECS data bus, L1b data bus is divided into 3 columns for ECS accessing and every column of L1b is 32-bit width. ECSAD(3..2) is used to distinguish 3 columns because the lowest two bits ECSAD(1..0) is always neglected. Corresponding with ECSAD(3..2)=3, there is a virtual fourth column which is fixed with X”0C0FFEE0”. The left ECSAD(26..4) exactly should be equal to L1b 23-bit address bus.