Strategy towards TDR: Single Phase Far Detector

Cold Electronics Consortium

Version 2.1 - DRAFT Date: 01/294/2018

This document outlines the strategy and important milestones leading to the Technical Design Report (TDR) for the design, development and validation of the Cold Electronics (CE) systems for the Single-Phase DUNE Far Detectors (FD). This document complements and supersedes the strategy document presented at the October 2017 LBNC meeting (DUNE DocDB-6658) for the choice of the ASICs to be installed on theFront End Motherboards (FEMB). The proposed strategy is based on the CE WBS document (DUNE DocDB-5612) and list of 2018-2019 project activities (DUNE DocDB-6458) developed by the consortium. The goal of the Consortium is to develop by the time of the TDR a baseline for the Cold Electronics with at least one technical solution that demonstrates a performance that meets the DUNE requirements, leaving open the possibility of alternatives for the ASIC chipset to be used on the FEMBs. If more than one solution meets the DUNE requirements the choice of the final set of ASICs (or single ASIC) to be used for the construction of the Single-Phase DUNE Far Detectors will be taken later in 2019 or early in 2020. In addition to pursuing the R&D program required to meet the goals related to the TDR, we will also develop a set of criteria for the final selection of the solution to be implemented in the Single-Phase DUNE Far Detectors, including consideration of the reliability of the proposed design. We will also continue the design of other components that have impact on other DUNE Far Detector subsystems (most important are the design of the cable plant inside the cryostat, including all the routing issues, and the finalization of the interface with the DAQ system), improve the description of interfaces with other consortia, and perform tests that demonstrate that the proposed design satisfiesy the DUNE requirements as well as those of the interface documents. When appropriate we will delay improving the design of detector components that have already been tested in protoDUNE until the final results of the analysis of its data are available. The rest of this document will discuss important design considerations and milestones leading to the TDR.

  1. Timeline

The milestones presented in this document follow the timeline below as set by the experiment leadership:

April 2018: Technical Proposal(TP)
April 2019: Technical Design Report

2019 & Beyond: Prototyping, Testing and Production

Late 2021 / Early 2022: Start Production of all the ASICs required for the Single-Phase TPC Far Detector

2022: Begin Installation of the Single-Phase TPC Far Detector

End 2024: Single-Phase TPC Far Detector commissioned

2026: Beam data taking with the Single-Phase TPC Far Detector

  1. Strategy and Design Considerations

This section summarizes the strategy and some important design considerations for the Single-Phase TPC Far Detector Cold Electronics. The section is divided in two main sub-sections: one for the ASICs, and one for the rest of the consortium’s deliverables.

2.1.ASICs

The strategy for the development, validation and testing of the Cold Electronics for the DUNE Far Detector was first approved by the Executive Committee on and described in DUNE DocDB-6658XXXX. It follows on from the recommendations of the Cold Electronics Task force (DUNE DocDB-2374). This report was discussed at the DUNE Executive Committee meeting on 5th June 2017 and three main points were agreed:

  • the existing cold ADC ASIC design would no longer be pursued and a new cold ADC solution would be developed;
  • the development of the new ADC should be a collaborative effort between more than one institution, to avoid a possible single point of failure;
  • if resources were available, an alternative solution should be investigated. This could be a single-chip solution or an alternative to the new baseline cold ADC (once chosen).

Below we update the original Cold Electronics Strategy document to include developments that have taken place after 5 October 2017the October 2017 LBNC meeting. Where appropriate we highlight the changes to the document.

2.1.1.Overall Strategy for Options

There are four potential solutions that are being considered:

  • Option 1: a new custom ADC ASIC, with the cold electronics system comprising: a final iteration of the existing frontend chip + a new custom ADC ASIC + the COLDATA ASIC.
  • Option 2: an integrated single chip solution based on the CRYO chip being developed by SLAC [update: this was originally referred to as the NEXO chip].
  • Option 3: a commercial ADC, replacing the custom ASIC;
  • Option 4: other custom ADCs, such as ATLAS ECAL ADC, replacing the custom ASIC in Option 1;

The collaboration strategy is to focus on two solutions. The baseline is the new custom ADC ASIC (Option 1), as recommended by the Cold Electronics Task Force. The alternative solution is the SLAC single-chip solution (Option 2). The baseline will be used for the cost estimates in the Technical Proposal, but the final choice for the far detector will be based on the relative performance of the two solutions. Until the new custom ADC solution is proven, the commercial ADC and ATLAS ECAL ADC will be retained as fall back options for the 3-chip solution.

Option 1: Custom ADC ASIC (baseline)

  • The choice of the custom ADC over, for example, a commercial option is motivated by a number of considerations, including the potential advantages of a solution using design rules for cold operation and the layout is understood by the consortium.
  • The Cold Electronics consortium will not assume that the existing FE chip meets the requirements for DUNE and will define a program of testing the FE chip to understand its contributions to the system noise, both in isolation and when coupled to the overall system.Status as of January 2018: The revision of FE ASIC is being finalized, both schematics and layout design are complete. The simulation with extraction is in progress, a bug in parasitic extraction tool has been addressed with Cadence support recently. A decision should be made soon on whether to submit this iteration for prototyping or whether to include further changes to improve the interface with the ADC ASIC.
  • The design study conducted in late summer concluded that the new ADC should be a 2 MSPS 12-bit pipeline ADC with foreground calibration implemented in 65nm CMOS. This chip will be designed by a collaboration between LBNL, FNAL, and BNL. Carl Grace of LBNL will be the lead engineer for the design.Status as of January 2018: the design of the analog to digital conversion engine is almost completely simulated. Some sections have transistor-level schematics, but most have only Verilog or RTL description. The back-end logic has been simulated in Verilog, translated to RTL, and synthesized. Work on the pad frame is starting. Design is also progressing on a band gap voltage reference and on the interface to the FE ASIC.It should be noted that all tests on the CDP1 prototype of the COLDATA ASIC were successful, both at room temperature and at LAr temperature; only a minor flaw was found in the implementation of the I2C protocol; the design of the full COLDATA ASIC is currently in progress. We are targeting a submission of the first version of the ADC for June 2018. The possibility of merging the ADC and COLDATA ASIC into a single ASIC is considered for a later iteration of the design that would take place in 2019.
  • (New relative to the original strategy document) Since the new ADC and the COLDATA ASIC both use the 65 nm we foresee the possibility of avoiding the interface between the two ASICs and merge their design into a combined ADC+COLDATA ASIC. The decision on proceeding with the merging of the two designs will be taken only upon successful prototyping of both designs, at the earliest in December 2018.

Option 2: SLAC CRYO chip (alternative)

  • The SLAC CRYO chip has a similar FE architecture to that developed by BNL for the existing FE chip. It combines frontend, ADC and data handling functionality on a single device, which has potential advantages. However, modifications will be required to optimize the noise performance for much larger capacitive load of the DUNE APAs. [update: this was originally referred to as the NEXO chip, this change has been made also in the following].
  • DUNE supports the deployment of resources to modify the SLAC CRYO chip to account for the different capacitive load. Status as of January 2018: the submission of the CRYO chip prototype is planned for the end of February. The chip uses the 130 nm technology, and it is designed using appropriate cryogenic models for operation at LAr temperatures. The implementation of the front-end, of the ADC engine, of the LDO regulator, and of the backend (including controls, PLL, encoders, serializers, and transmitters) are all complete. Work is on progress for the biasing and reference voltage generation circuits, and for the integration of the analog and digital blocks. The LDO regulator will be further optimized to reduce the noise after a full simulation of the front end. The final layout of the analog and digital sections is in progress. We expect to have first results on the CRYO prototypes and their suitability for use in DUNE by June 2018.
  • It is not a priori clear that the SLAC CRYO solution will deliver the required performance. However, from the systems-engineering perspective, a single device may minimize other risks.
  • If the SLAC CRYO chip were adopted, there would need to be a clear plan for how multiple institutions would be involved in the final design and evaluation to mitigate the risks of relying on a single institution.

Option 3: Commercial ADC (risk mitigation)

  • The commercial ADC option is being studied by SBND and DUNE will monitor these studies. This is not a preferred solution, but it is considered as a risk mitigation strategy until the custom ADC has been developed and validated.
  • There are concerns about the practicalities of the commercial ADC option for DUNE. It would require the purchase of a very large number of chips prior to long-term testing and evaluation in order toavoid potential changes in the production process and/or packaging. The commercial ADC option is therefore only considered as a risk mitigation strategy and will be discarded when a custom ADC has been validated.
  • Status as of January 2018: we are following the progress made by SBND (David Christian is a reviewer for SBND) and expect to have a full characterization of a commercial ADC in time for a first selection of options to be studied with a TPC prototype in June 2018.

Option 4: ATLAS upgrade ECAL ADC chip (risk mitigation)

  • The ATLAS ADC for the ECAL upgrade is not a preferred solution, but it is considered as a risk mitigation measure until the custom ADC has been developed and validated.
  • The ATLAS ADC is being developed for warm operation using ATLAS resources. Columbia will be provided with some limited project resources to evaluate its operation in the cold.
  • Status as of January 2018: Work has started at Columbia University on testing both the 130 nm and 65 nm versions of the ATLAS ADC chip, with an expectation that the initial testing at LN2 temperature (close to that of liquid Argon), will be completed by June 2018.

2.1.2.Testing Options

There are five (currently planned) options for testing the cold electronics chain:

  • CERN Cold Box: this provides a system test in the cold (gas) with a full-scale APA. DUNE plans to produce seven APA planes, six for protoDUNE-SP and one for the Cold Box, to provide a long-term test facility.
  • ProtoDUNE: the existing implementation of the cold electronics (FE + ADC) will be tested in the first year(s) of protoDUNE operation. It provides a full-system test in the TPC environment, but not with the final version of the electronics. The comparison of the noise in protoDUNE-SP with that seen in the Cold Box will establish the level of equivalency of testing in the Cold Box with the full TPC.
  • LArIAT: is an easy to use system that would allow DUNE to test future versions of the cold electronics systems in a small liquid argon TPC. The shorter wires mean that the capacitive load is different from a full-scale APA.
  • ProtoDUNE (Phase 2): in principle it is possible to replace the cold electronics boxes in ProtoDUNE-SP. This is not a trivial operation, but access through the manhole is possible. One installation option for the new cold electronics to be installed from outside the field cage. This appears to be possible from the Jura side of the detector. DUNE wishes to retain the option of second phase of protoDUNE operation as a possible test of the final system in 2020 or 2021, but this may not be possible due to lack of resources.
  • SBND: could provide an option for a long-term test of DUNE cold electronics. However, it is not an ideal proxy because the SBND APAs are somewhat smaller and do not use wrapped wires. The current plan is for SBND to be operational in late-2019/early-2020. SBND intends to make a decision on electronics in 2018. SBND could provide risk mitigation in the event of the unavailability of protoDUNE-SP, but timing is an issue. A second phase of SBND operations (with replaced electronics) after the physics run would come too late for DUNE. If the start of SBND operations were delayed to 2021 for external reasons, it could provide a test bed for the DUNE Far Detector electronics. This is not the preferred option for DUNE and would require the DUNE final design to be ready relatively early.

Status in January 2018: we think that most likely we will be using a protoDUNE APA in the CERN cold box and a newly constructed APA to be housed in a new LAr cryostat at Fermilab for qualifying the different prototype ASICs prior to the TDR. We are planning to build a new APA (with reduced size compared to DUNE) reusing the same boards that are used for protoDUNE (the size reduction will be accomplished by using a smaller number of boards). We expect this new APA and the new cryostat to be available toward the end of 2018, and we are targeting the fabrication of new front-end motherboards, housing the latest version of the FE ASIC, the first prototype of COLDATA, and various ADC prototypes (or just the SLAC CRYO ASIC) for the Fall of 2018, such that tests in both the cold box at CERN and with the new APA in the new cryostat at Fermilab can be done and analyzed prior to the submission of the TDR.

2.1.3.Testing Strategy and Decision Tree

By the end of 2017, the Cold Electronics consortium will establish the criteria for deciding whether to adopt the baseline solution (2 or 3 chips) or the alternative single-chip solution.Status in January 2018: we have not yet produced a document that contains all the details of the selection criteria to be used to decide among the multiple options for the ASICs that are being considered. A first version of the document, covering only performance issues will be made available has been made available during prior to the February DUNE Collaboration Meeting. This version will be finalized and submitted to the LBNC by Monday 5 February 2017. We plan to have a second version of this document that will also cover reliability issues in time for the May DUNE Collaboration meeting and the May meeting of the LBNC. We will start a working group including engineers with relevant expertise to further develop these selection criteria (this group will be announced during the February DUNE Collaboration Meeting).

Prior to the TDR, DUNE will plan for systems tests of the baseline and alternative options in both the CERN Cold Box and in the LArIAT cryostat with a small liquid argon TPC. The Cold Box tests establish performance of the electronics coupled to a full-scale APA in a correctly grounded environment, but in a gaseous environment, without TPC drift. LArIAT would provide tests in an operational LAr-TPC, but at a much smaller scale. The technical feasibility of this plan still needs to be established and will be investigated before the end of 2017. The testing strategy and outline decision process is summarised below:

  • End of 2017: current ProtoDUNE-SP electronics tested on an APA in the CERN cold box. This will establish the noise level in the existing system in this environment. Status in January 2018: the first two APAs of protoDUNE have been equipped with electronics and tested in the cold box at CERN where temperatures around -11000oC have been reached. While data from these tests is being still analyzed, preliminary results indicate that the performance obtained with the protoDUNE electronics is in line with expectations, indicating that the DUNE requirements can be met. Coherent noise generated by other detector components has been observed and addressed (from the photon detector, cured with the addition of a resistor on the photon detector electronics; from RTDs, cured with proper grounding of the RTD connections at the cryostat flange).
  • Early 2018: standalone tests of SLAC CRYO chip. This will establish whether this chip might provide a route to the required low noise operation for the DUNE far detector. Status in January 2018: we expect results from the initial testing of the CRYO chip late in Spring 2018.
  • Technical Proposal (Q2 2018): the technical proposal will include the baseline and alternative options, unless initial testing of the SLAC CRYO chip excludes a viable path to the DUNE requirements.Status in January 2018: we are planning to discuss all the options mentioned above in the technical proposal, and to have a first review of tests of the CRYO ASIC, of commercial solutions, and of the ATLAS ADCs in June 2018. Results from the new combined ADC will be available later in Summer 2018.
  • Q3 2018: operation of current ProtoDUNE-SP electronics in the full detector. This will provide a systems-level test of the existing solution and will establish the degree to which testing in the Cold Box can be used to predict the full performance.
  • Q3 2018: standalone tests of new custom ADC ASIC.Status in January 2018: we think that this milestone can still be met.
  • Late 2018: test the current electronics in LArIAT to establish a reference point.
  • Early 2019: tests of baseline and alternative options in both the CERN Cold Box (full size APA in cold gas) and in LArIAT (small TPC in liquid argon), prior to the TDR.Status in January 2018: we think that this milestone can be met, and we will be using a new TPC in a new cryostat at Fermilab for performing these tests.
  • Early 2019 [new]: the list of milestones presented below foresees the possibility of a second design iteration for all the ASICs, in case they come close to meeting the DUNE requirements. This also involves the possibility of having an ASIC that combines the functions of the ADC and of COLDATA. It is assumed that (with the exception of a combined ADC/COLDATA) this second version of the ASICs will have the same pad layout of the first one and that this will allow us to reuse the FEMBs for testing.
  • Technical Design Report (Q2 2019): at this time, we will have results from protoDUNE-SP and the tests of the baseline and alternative options. If the performance of the baseline and alternative options are similar, e.g. within 20% in terms of Equivalent Noise Charge, both will be presented in the TDR. In this case, the DUNE collaboration will initiate a technical review (based on the previously agreed criteria) to decide which option is presented as the baseline for the DOE CD-2/3b review. If there is a clear difference in performance in the testing environments, e.g. one option has 50% higher ENC, only one option will be presented in the TDR.
  • 2020: DUNE will plan for a full system test of the final cold electronics options presented in the TDR to take place during 2020. ProtoDUNE is the favoured choice, at this stage.

2020-2023(?): A long-term, large-scale stability test of the final cold electronics, in order to test reliability and longevity, will take place in the period 2020-2023. The testing plan will be developed by Cold Electronics consortium during 2018.