ATLAS Project Document No: / Page:1 of 1
Fehler! Verweisquelle konnte nicht gefunden werden. / Rev. No.: Fehler! Verweisquelle konnte nicht gefunden werden.
/ Technical Description of the Interlock Circuit and System of the ATLAS Pixel Detector
ATLAS Project Document No[A1]: / Institute Document No[A2]. / Created [A3]: Sept, 6 2001 / Page: 1 of 15
ATL-IP-ES-0041 / Modified [A4]:February 07 2004 / Rev. No [A5]: 1.2
Abstract [A6]
This document describes the realization of the interlock system as it is under investigation for the ATLAS pixel detector, where necessary the reports on relevant measurements are included. The design is based on the choice of the temperature sensor: a 10 k NTC resistor. A modification for the use with other NTC resistors is possible.
[A7]
Prepared by[A8]:
Susanne Kersten
Peter Kind / Checked by:
PRR Feb. 2002 / Approved by:
Distribution List[A9]
Pixel Detector Distribution list
ATLAS Project Document No: / Page 1 of 15
ATL-IP-ES-0041 / Rev. No.: 1.2
History of Changes
Rev. No. / Date / Pages / Description of changes
Draft
1.0
1.1
1.2 / 6-Sept-01
5-Feb-02
29-April-03
7-Feb-2004 / All / Draft release for comments
Minor modifications, last measurements included
I-box board modified for mounting in crates, doco updated accordingly
further minor modifications on Ibox board for rack installation
ATLAS Project Document No: / Page 1 of 15
ATL-IP-ES-0041 / Rev. No.: 1.2

Table of Contents

Table of Contents

1Introduction

2The Temperature Sensor

2.1Correlation between the NTC resistance and the temperature

2.2Spread of the NTC resistors

2.3Long-term Stability

2.4Irradiation Tests

3Interlock Box

3.1Electrical circuit

3.2Measurements on the electrical performance

3.3Build-in Test Features

3.4Irradiation Tests: Pre-selection

3.5Test in magnetic Field

3.6Casing

4Appendix

4.1References

4.2Schematics of the interlock box

Technical Description of the Interlock Circuit and System of the ATLAS Pixel Detector

1 Introduction

The aim is to have a pure hardware based temperature control system, which creates in cases of heat ups of the sensitive pixel detectors a logic signal, which can be used to switch off the related power supplies. This interlock system is planed as an “emergency exit” if the supervisory detector control software fails for whatever kind of reason.

For the temperature sensor a 10 k NTC (negative temperature coefficient) resistor is chosen, on which the design of the interlock electrical circuit is build up. A comparator / discriminator unit is the base element of the interlock circuit. An overall tolerance limit of < 1K is acceptable for our application.

2 The Temperature Sensor

The requirements on the temperature sensor are described in [1]. As NTC resistors typically own a relative change of their resistance of ca. 4 % per Kelvin, they were chosen. The type Semitec 103KT1608-1P from Ishizuka, Japan is available with R (25 C) = 10 k  1 % and B (25/85) = 3435 K (see below, formula 1), tolerance of the B value: 1%. It is a SMD (0603) component. A further advantage is its glass coated package, avoiding problems due to irradiation.

A batch (same lot nr.) of 4000 sensors, of the type mentioned above was bought. For the measurements described in the following, samples from this batch were taken.

2.1 Correlation between the NTC resistance and the temperature

Besides the negative temperature coefficient, one has to consider the fact that the resistance of the NTC sensor is a non-linear function of the temperature. A first approximation is given by:

R(T) = R25 exp (B(1/T – 1/T25)) (1)

R(T) / Resistance at temperature T [K]
R25 / Resistance at 25 C
T25 / 298,15 K
B / 3435 K

The B-value is specific for each sensor type and is normally calculated from the resistance at 25 and 85 C. Therefore formula (1) above describes the behaviour exactly only for these two temperatures. Due to the tolerances of the B value, the error of the temperature has a “butterfly” like shape with its minimum at 25 C, see colored band in Fig. 1.

T [C] / R(T) [k] / Error [K]
+25 / 10.00 /  0.3
+10 / 18.25 /  0.4
0 / 28.16 /  0.5
-10 / 44.72 /  0.5

Table 1: Typical values for the Semitec 103KT1608-1P, taken from the data sheet

In order to determine the temperature T [C] from a measured resistance R, the Steinhart-Hart equation should be applied:

1/T = A0 + A1 * ln (R/) + A3* (ln(R/))3 (2)

A0 [1/K] / 0.66103 * 10 -3
A1[1/K] / 0.28957 * 10 -3
A3[1/K] / 0.30692 * 10 –7

Table 2: coefficients for the Steinhart-Hart equation (determined for the selected batch)

For a precise determination of R, the voltage drop across R and the reference voltage (see section 3.1) should be measured.

2.2 Spread of the NTC resistors

A set of 16 NTC sensors was taken, their resistance values were measured in a thermobath (  0.1K) in the range between –20 and +25 C. The temperature indicated by the NTCs was determined by using formula (2), this value is compared to the temperature measured by the thermobath. Fig. 1 shows that the spread for the selected sample is inside the expected limits given by the data sheet, (coloured band).

Fig. 1: spread of 16 NTC resistors

2.3 Long-term Stability

The long-term stability of the temperature sensors was studied by an accelerated ageing in an oven at 100 C for one week. According to the Arrhenius equation the thermal acceleration factor TAF was calculated:

TAF = exp ( EA/k(1/TN –1/TS) ) (3)

EA / activation energy = 1.0 eV for ceramics
K / Boltzmann constant
TN , T S / Temperature in [K], TN = 273 K, TS = 373 K

Assuming a foreseen operating temperature of 273 K, this gives a TAF of 89012, which means 1 week in the oven simulates 1700 years. The resistors were measured before and after ageing in a thermobath, formula 2 was used then to calculate the temperature. The maximal observerd differences are +0.25 K and –0.1 K, Fig. 2 shows typical results. Values on the complete set of 16 NTC sensors can be found in [2]. The differences of sensor 15 and 16 in the low temperature region (– 20 to –18 C) of up to 0.25 K might be caused by bad thermal contacts resulting in a bad thermal equilibrium specially in the beginning of the measurement.

Fig. 2: Differences in the NTC temperature measurements before and after ageing

2.4 Irradiation Tests

A sample of 12 NTC resistors was irradiated with 24 GeV protons at the T7 beam of the SPS, CERN. The reached fluence varied depending on the position in the beam between (0.73 to 2.05) 1015 p/cm2. This corresponds to the fluences to which the front end chips, which will be located in the same position, are irradiated. The resistors were measured before and after irradiation in a thermobath, formula 2 was used then to calculate the temperature. As can be seen in Fig. 3 the spread of the NTCs does not deteriorate with irradiation. (Due to bad electrical contacts one sensor was outside the limits from the beginning.) The maximal measured differences for individual sensors are 0.2 C, Fig. 4 shows typical results, the complete overview on all 12 resistors can be found in [2], see also the comments in the previous subsection.

Fig. 3: spread of the NTC resistors before (left) and after irradiation (right) with 24 GeV protons

Fig. 4: NTC temperature measurements before and after irradiation with 24 GeV protons

3 Interlock Box

3.1 Electrical circuit

  • Diagram

Fig. 5 Electrical schematic of the Interlock Box

Fig. 5 shows the realization of the interlock circuit. A clean reference voltage is created by the reference section. The signal from the NTC is then compared to different thresholds, the op-amps acting as discriminators. The following NOR-gates create a pattern of two bits, representing the different error conditions, see table 3. Negative TTL compatible logic is employed, active low, (“0” = 0 V, “1” = 3.3 V).

In order to reduce the influence of noise, a hysteresis of ~1 K is foreseen between the setting of the alarm signal and its reset.

In the actual design there is a 5V regulator for the analog partsand a 3.3 V regulator for the NOR-gates. To prevent short circuits and to improve the stability for long cables, each gate output has an 1 kΩ resistor. These components are not shown in Fig.5.

Tlow / Thigh
Okay / 1 / 1
Temp. too high or short cut / 1 / 0
Temp. too low / 0 / 1
Sensor broken, power failure / 0 / 0

Table 3: output bit pattern of the Interlock Box

  • Self heat up

The foreseen NTC sensor has a dissipation constant of 1 mW/K (in air). In order to keep the self heat up in the range of 0.1 K (corresponding to 100 µW), the series resistor R1 is set to 10 k (RNTC = 37 k @ -6 C  47 k @ 2.5 V).

  • The Shooting Point

The temperature high warning (shooting point), the temperature low warning and the error signal are determined by the resistors, which are mounted on the separate small PCB board, which can easily be exchanged. These settings apply to all 16 channels of the Interlock Box.

With R1 = RH1 = 10 k, R2 = 3.9 k, R3 = 1 M, see Fig. 5, the shooting point is determined by RH2. Adapting the shooting point to a desired temperature T, which corresponds to a value RNTC, see section 2.1, a first approximation gives RNTC  RH2. The following equation can be used to find the precise value for RH2:

(4)

Similar equations can be calculated for RL2 and RE2, which fix the low temperature level and the error condition (sensor broken).

  • Precision of the Interlock Box

The precision of the Interlock Box is mainly given by the error of the comparators. The offset voltage of the Op-amps (max. 0.5 mV) and the tolerances of the resistors (R1, RH1, RH2: 0.1%, R2…R7: 1%) which are building the voltage dividers for the comparators, must be considered. Assuming a NTC resistor at + 10 C, ca. V = 20 mV are corresponding to T = 1K. By this the precision of the Interlock Box, caused by the tolerances of its components, can be estimated to  0.16 K. This is the maximal limit, not a standard deviation.

  • Noise filter

In order to reduce the influence of noise (caused by unshielded cable for example) the input of the Interlock Box is equipped with a low pass filter, built by R8 and C1.The reaction time (time constant 0.47 s) must be considered.

  • Power consumption

The required power depends on the load on the outputs, with no load on the outputs it takes typically 2.2 mA at 5V. As in the okay status all 32 outputs will be active, low current opto couplers should be used in the input of the logic unit or any other subsequent electronics. With 1 mA opto couplers the resulting power consumption will amount to ca. 35 mA, a max. value of 100 mA should not be exceeded. (Since the 3.3 V regulator power dissipation is limited to 500 mW for the TO-92 package at 100 mA the voltage drop should not exceed 5 V, i.e. input voltage maximal 8.3V, repsectively at 35 mA U should be below 18 V.)

3.2 Measurements on the electrical performance

  • Measured precision of shooting point and its reset

Fig. 6 shooting point and its clear for 2 Interlock Boxes (the rings representing the error)

The shooting point and its clear were determined with a precision multiturn potentiometer. The results for 3 Interlock-Boxes can be seen in Fig. 6 and 7. The vertical lines are representing the theoretical expected values for the shooting temperature and its clear, the colored band indicating the expected spread due to the tolerances of the electronic components of < 0.2 K.

  • Test with a long cable in the input

Fig. 7: shooting point and its clear for short and long cable in the input lines

Fig. 7 shows shooting point and its clear measured with a short and a long cable in the input lines (60 m, AWG 28, 2 x 12 ). The resistance of the input line causes a small shift, for later application one might have to consider the sum of the NTC and the cable resistance, when calculating the shooting point.

  • Compatibility with the ELMB

At first the shooting point and its clearing was measured using a precision multiturn potentiometer for the channels of one Interlock Box (I Box Nr. 15) in standalone. In a second step the ELMB was connected in parallel to the Interlock Box, the ADC (5V range) was permanently scrolling. No shift in the shooting point of the Interlock Box nor its clearing could be observed, see Table 4. (mean value of 50 measurements, maximal deviation + 0.01 and – 0.02).

Ch Nr. / Shooting point - without / Clear - without / Shooting point with ELMB / Clear with ELMB
1 / 17.99 / 18.63 / 18.00 / 18.63
2 / 17.98 / 18.62 / 17.99 / 18.62
3 / 17.99 / 18.62 / 18.00 / 18.63
4 / 17.98 / 18.62 / 17.99 / 18.63

Table 4: shooting point and its clearing without and in parallel to the ELMB

(all values given in k)

  • Compatibility between DAQ and DCS

In order to study the crosstalk between DCS and the data acquisition chain, a detector module equipped with its flex hybrid circuit (including the NTC) was readout while the components of the detector control system were connected and operated at the same time (Interlock Box and ELMB with its CAN-bus connection to a PC). For comparison a full scan over all 16 front end chips was first performed without any connections to the NTC and the DCS components. The noise of all pixel cells was determined, Fig. 8 gives the results for each front end chip. As to be seen the spread between single chips is quite large, giving mean values ( standard deviation) of (307  71) e- for the reference measurement and a mean value of (293  58) e- while DCS was performing its monitoring loops.

Although these measurements as aspected do not show an increase of noise due to DCS, this test should be repeated with the next generation of front end chips as the stability of the detector module was quite small. It also should be investigated then whether the filtering capacitor as connected for these measurements (100 nF in series to the NTC) is finally required.

Fig.8: Noise performance with and without DCS connections

3.3 Build-in Test Features

  • A testsignal can be applied to trigger the temperature high warning signal of all channels simultaneously.
  • As in increase in the power consumption might indicate problems due to irradiation the supply current can be monitored.
  • The temperature detected by the NTCs is also monitored by the ELMB, this gives an additional possibility to trace problems.

3.4 Irradiation Tests: Pre-selection

Three types of possible problems were studied in order to qualify the electronics: damage due to ionising (“total ionising dose”: TID) and non ionising radiation (“non-ionising energy loss”: NIEL) and single event effects (SEE). The expected simulated radiation levels are given in [4]. (As there are no values available for the ATLAS cavern, the numbers for MDT barrel 3 were taken.) In order to determine the “radiation tolerance criteria” for unknown batches, several safety factors are added, table 5 summarizes them for the Interlock Box based on the calculations described in [4]. All components were at least irradiated up to these levels.

10 years operation in ATLAS
RTCTID / 93 Gy
RTC NIEL / 4.8 1011 n/cm2 (1 MeV)
RTCSEE / 9.22 1010 h/cm2 (> 20 MeV)

Table 5: “Radiation tolerance criteria” for the Interlock Box

As a pre-selection 3 kind of irradiation campaigns were performed up to the limits given in Table 5:

  • TID studies with a 2.104 Ci Co- 60 source;
  • A neutron irradiation at the CEA Valduc, France, research reactor with an energy range up to a few MeV with maximum intensity at 0.7 MeV;
  • SEE studies at the 60 MeV proton beam of UCL, Belgium.

Usually five to ten devices were irradiated per campaign. During all irradiation tests the components were powered, monitored and checked online for performance and power consumption.

During a former irradiation the old Op-amp (LMC6064) turned out to be a weak component. The reaction time to a high temperature status increased unacceptably. Further it was observed that the amount of destruction depends on the output voltage the op-amp was set to during the test and it seemed to depend also on the fact whether the op-amp had to switch during irradiation or not. Therefore the new selected Op-amp was operated in 2 different ways during irradiation: dynamically and statically. As the offset voltage of the op-amp is critical to the accuracy of the circuit (1 mV corresponds to 1/20 K) this quantity was measured for several input voltages. Figure 9 shows a typical result, indicating that no deterioration is expected. The coloured band represents the acceptable variation in our application. All other devices did not show any problems, either during or after irradiation. Table 6 summarizes the components which finally passed the three irradiation tests, all test results can be found in [3].

Fig. 9: Offset Voltages of the OPA-336 (TID: 100 Gy)

For the study of single event effects additionally a special program was developed to monitor the complete circuit for transients or other temporary changes in the output. They were never observed. The shooting points of the interlock circuits were measured before and after the irradiation, Fig. 10 compares the results for one of the four tested Interlock Boxes.

Fig. 10: shooting point before and after irradiation (60 MeV protons)

Selected device / TID / NIEL / SEE
Op-Amp / OPA336N / 5 / 5 + 5 / 6 + 2
4 fold Op-Amp / OPA4336EA / 6 / 6 + 6 / 4 + 24
NOR-gate / MC74LCX02D / 7 / 5 + 5 / 6 + 16
Analog switch / TC4S66 / 5 / 5 + 5 / 6 + 2
Voltage reference / AD680JT / 7 / 2 + 8 / 3 + 2
Voltage regulator / LE33CZ / 3 + 7 / 5
Capacitors / Ceramicmulti-layer / 5 / 5 / 6
Resistor network 0.1% / KPC RIA N16 G103 / 3 / 2 + 8 / 2

Table 6: Components which passed the pre-selections

Table 6 summarizes the components which passed the pre-selections, number of irradiated devices are listed in the corresponding columns, the second number for SEE refers to the components which were mounted inside the complete Interlock Boxes. Actually the numbers of tested devices for SEE can be added to the TID numbers as 1011 60 MeV protons deposite about 140 Gy, which is more than required by [4].

3.5 Test in magnetic Field

One Interlock Box was placed in a magnetic field of 1.5 T, three different orientations were investigated. The shooting point and its clearings (back to okay) were measured, no dependence could be observed, see Fig. 11.

Fig. 11: Behaviour in magnetic field (measured at CERN by H. Hufnagel)

3.6 Casing

The Interlock Box is a ca. 10 x 10 cm board and is designed for installation in 3U high crates. Further details, like layout, connector pin assignments etc. can be found in [5].

4 Appendix

4.1 References

[1] Requirements for Interlock Circuit and System of the ATLAS Pixel Detector, ATL-IP-ES-0040

[2]

[3]

[4] ATLAS Policy on Radiation tolerant Electronics, ATC-TE-QA-001

[5] Pixel PP3 Patch Panels desgin ATL-IP-ES-0075

4.2 Schematics of the interlock box

channel 5-16 are identical

[A1]1Enter No

[A2]1Enter No

[A3]1Enter Date dd/MM/yyy

[A4]1Enter Date dd/MM/yyy

[A5]1Enter No

[A6]1Enter text of abstract

[A7]1Enter text of abstract

[A8]1Enter Name, Institute, E-mail

[A9]1Enter Number/Title