Modeling of Electron Substrate and Gate Current for Single-Drain Buried-Channel pMOSFETs
Chorng-Jye Sheu
Abstract –In this paper, we present a non-local electron substrate and gate current model for single-drain (SD) buried-channel (BC) pMOSFETs. A non-local impact ionization coefficient with characteristic length dependence both in exponential term and pre-exponential factor is used in the substrate current model. The gate current model is developed by originating a modified lucky electron concept including the quantum-mechanical tunneling effect in parallel. The channel electric field is first calculated by using an analytical pseudo-2-D MOSFET model, and the spatial distribution of electron temperature along the channel is then derived by using a simplified energy balance equation. From non-local impact ionization coefficient and electron temperature, the non-local electron substrate and gate current can be derived. This model is a time-saving CAD model and is physics transparent for single-drain buried-channel pMOSFETs.
I. Introduction
The importance of p-channel MOSFETs has been increasing remarkably because of the growing extension of CMOS device usage in VLSI technology. It was reported that hot-carrier generation and gate injection can be problems even in buried-channel pMOSFETs, as well as in surface-channel nMOSFETs. Hot carriers are known to cause long-term threshold voltage and transconductance shifts, drain-sustaining voltage lowering, internal latchup, and so on [l]. Several works have been reported on buried-channel and surface-channel pMOSFETs. The main causes of the degradation in these devices are trapped electrons injected into the gate oxide, and the device lifetime has been evaluated using the gate or substrate currents [2].
It has been well accepted that substrate current, arising from impact ionization in MOSFETs is an important measure to estimate device degradation or device lifetime due to its high sensitivity to hot carriers. It is essential to investigate the behavior of hot carriers in highly inhomogeneous fields because the impact ionization events occur in the channel near the drain where internal electric field increases exponentially [3]. It is widely recognized that the pMOS hot-carrier degradation has a close correlation with the electron gate current injection, which normally happens at high VDS and low VGS (≈VT). Therefore, it is essential to have an accurate gate current injection model for predicting the pMOS hot-carrier lifetime at operation conditions [4].
As VDS > VGS hot-electrons and hot-holes can be generated. Drain avalanche hot carrier injection (DAHCI) into the gate oxide can occur. Since the source of electrons in pMOSFETs is from impact ionization process which produces electron substrate current. The hot-electrons are most generated in the drain-side channel at low gate voltage stress condition, hence the electron gate current can be calculated simply from electron substrate current.
Because of the complicated BC current conduction, only few analytical models have been proposed to describe the BC pMOSFET drain, substrate and gate current. In the light of the deficiency in literature about the model of BC pMOSFETs, therefore we in this paper develop a new complete non-local electron substrate and gate current model for BC pMOSFETs. The buried-channel nature of device physics and a modified non-local impact ionization coefficient with characteristic length dependence both in exponential term and pre-exponential factor [3], [5] are used in the substrate current model. In conjunction with a previous work [6], a new lucky electron gate current model by improving the conventional lucky electron model to include the Fowler-Nordheim tunneling (FNT) and direct tunneling (DT) gate current components will be created. This work forms a pseudo-2-D, non-local, and time-efficient substrate and gate current model, and it provides physical insights into the substrate and gate current.
II. Model Development
In this section, we modify a non-local impact ionization coefficient with characteristic length dependence both in exponential term and pre-exponential factor in the substrate current model and develop a modified lucky electron model for calculating the gate current in single-drain buried-channel pMOSFETs.
An earlier study [3] introduced the concept of the effective electric field in order to explain the lagged electron temperature caused by the non-local effect. Higman et al. also reported a non-local impact ionization coefficient [6] in which only pre-exponential factor has characteristic length dependence. In this work, we are going to combine these two models to develop our new expression of impact ionization coefficient where the characteristic length is associated with the device parameters of buried-channel pMOSFETs.
The electron gate current comes from energetic electron which are generated by hole impact ionization and drain avalanche hot carrier injection (DAHCI) into the gate oxide can occur in buried-channel pMOSFETs. The lucky electron concept of channel hot-electron injection (CHEI) in n-channel MOSFETs will be adopted to model the electron gate current for drain avalanche hot carrier injection (DAHCI) into the gate oxide in buried-channel pMOSFETs. In this work, we also extend the conventional lucky electron model to incorporate the effect of Fowler-Nordheim tunneling and direct tunneling.
In what follows, we first calculate the spatial varying electric field along the channel and the drain current IDS from a previous work [7], then we develop the expression of non-local impact ionization coefficient and formulate the substrate current model in subsection A and the tunneling probability useful for the lucky electron model and the gate current model in subsection B.
A. Substrate Current Model
Due to the rapid change in the electric field, energy equilibrium between the electrons and the lattice may not be reached. Under this situation, the non-local effect is very important—the ionization coefficient is not only related to the electric field but also dependent on the shape of the electric field, which can be characterized by a characteristic length. From [3] and [5], the non-local impact ionization coefficient can be re-expressed as
(1)
where y is the direction along the channel, Ey is the channel electric field, g and B0 are constant and l0 is the energy relaxation length. The characteristic length, ls, is given by [7]
(2)
where εs is the permittivity of silicon, XI and XP0 are the depths of implanted channel and depletion region in the substrate, Co is the gate oxide capacitance per unit area, xs is a fitting constant and ho is defined as in [7].
According to the non-local impact ionization coefficient described in Eq. 1, the non-local substrate current shown in Fig. 1 can be derived as
(3)
where L is the channel length and IDS is the drain current of buried-channel pMOSFET.
B. Gate Current Model
Fig. 1. Cross-sectional view of a buried-channel pMOSFET. The series of probabilities in the model are illustrated.
Since the injection of electrons into the gate oxide is the driving force of the hot-carrier degradation in pMOSFETs. Modeling of electron gate current in pMOSFETs is important. Unlike nMOSFETs, pMOSFETs exhibit the largest gate current when biased in the saturation region at low VGB. The gate current of pMOSFETs results from electron rather than hole injection into the oxide because electrons have a longer mean free path, and the Si/SiO2 barrier height is lower for electrons and the vertical field favors electron injection. The electron gate current for buried-channel pMOSFETs can be written as
(4)
where W is the channel width, L is the whole channel length, Jg is the electron gate current density. Recently we have developed a non-local gate current for calculating electron gate current in silicon-on-insulator pMOSFETs [6]. Now we extend the above equation to describe the electron gate current in buried-channel pMOSFETs. The holes in the channel are accelerated by the channel electric field to initiate the electron-hole pair generation, and the hot-hole loses its kinetic energy during the impact-ionization process and flows to the drain. The impact-generated electrons flow to the source and part of them are injected into the gate oxide and becomes electron gate current. The lucky electron model for channel electron injection is based on a number of probabilistic arguments shown in Fig. 1. We can refer to Fig. 2 where a qualitative energy band diagram for electron tunneling after the pinchoff point is shown. The lucky electron gate current density Jg is given by
(5)
where P1e is the probability that an electron has an energy between E and E+dE, P2' is the re-direction probability of
Fig. 2. Energy band diagram of a poly-gate-SiO2-silicon system near drain side of a BC pMOSFET.
an electron per unit length, P3' is a scattering probability factor weighted by the electron concentration in the inversion layer. P1e is given by
(6)
where Tl is the lattice temperature, λe is the mean free path for energy relaxation and kB is the Boltzmann constant. In high channel electric field Ey, electron-hole pairs are generated through hole impact ionization. The hot-hole generated electrons are accelerated towards the source with decreasing electric field strength. Here we adopt the local field approach for the hot-hole generated electrons because they encounter the accelerating electric field with decreasing strength and it is simple for mathematical manipulation. With this approach, it is easier to model electron injection in pMOSFETs. The hot-carrier generated electrons are treated as carriers with electron temperature Tn equal to Tl +λeEy2q/(5kB) [7]. Pox is the probability that electrons can arrive at the gate electrode from the Si/SiO2 interface. By extending the WKB approximation for the two different band-bending cases, the probability for Pox is summarized as:
(7)
where fB0 is the intrinsic potential barrier height at Si/SiO2 interface and fB is the maximum potential barrier height in the gate-oxide, and it includes the Schottky barrier lowering effect. Vox is the gate oxide voltage drop and Eox is the electrical strength in the gate oxide layer. TD″, TFN″, TTI″ are respectively the DT, FNT, and thermionic emission rate and are the same as those defined in [6]. P2' is the redirection probability of an electron per unit length. P3' is a scattering probability factor weighted by the electron concentration in the inversion layer. And
(8)
where λox is the mean free path in the oxide, tox is the gate-oxide thickness and x1 is the distance from the Si/SiO2 interface to the classical turning/entering point.
III. Model Verification
A. Drain Current
To calculate the substrate and gate current, we first calculate the drain current IDS, free carrier charge density and channel electric field using the published model [7], and electron temperature using the method mentioned in the previous work [6]. Fig. 3 shows the modeled and experimental [8] output characteristics of a buried-channel pMOSFET with L=1.2 μm, tox=30 nm and the substrate doping is 4×1016 cm–3. The figure indicates a good agreement between experimental data and modeled results. In modeling of the drain current, the basic device parameters including some fitting parameters will then be extracted out and these parameters will be used in the modeling of substrate and gate current.
Fig. 3. IDS-VDS characteristics of a BC pMOSFET with L=1.2 mm, tox=30 nm.
Fig. 4. Modeled and measured [8] substrate and gate currents of a BC pMOSFET with L=1 mm, tox=20 nm.
B. Substrate and Gate Current
By using the same parameters extracted from Fig. 3, it is shown in Fig. 4 that with this consistent model good agreement is achieved between measured and simulated substrate and gate currents over a large range of bias conditions where Vt is the threshold voltage.
To model the substrate and gate current at low VGS, a drain current model valid in subthreshold region should be used. Fig. 5 shows the measured [1] and modeled drain current and electron substrate and gate currents with one
Fig. 5. Modeled and measured [1] substrate and gate currents in a BC pMOSFET as a function of drain and gate voltage with L/W=0.9/19 mm, tox=16 nm.
set of parameters. The BC pMOSFET is with L/W=0.9/19 mm, the gate oxide thickness is 16 nm where |VDB|=6 V. As can be seen, our model can describe the substrate and gate current around subthreshold region.
III. Conclusion
Analytical and complete electron substrate and gate current model for buried-channel pMOSFETs are derived and are verified through experimental data. The non-local impact ionization coefficient implemented in this paper demonstrates that the new coefficient with dependence of characteristic length of buried-channel can predict substrate current correctly. The gate current is the sum of thermionic emission, FNT and DT gate current components. This model gives the device physics of modeling substrate and gate current. To our knowledge, this is the first time-effective device model in the literature with the capability of calculating the drain, substrate and gate currents simultaneously for buried-channel pMOSFETs with reasonable accuracy.
Acknowledgement
This work was supported by the National Science Council, Taiwan, R.O.C. under Contract NSC 95-2516-S-270-001-. The author is particularly indebted to Prof. Sheng-Lyang Jang for many valuable suggestions on developing model.
References
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