Boston University Dept. of Electrical and Computer Engineering

SC312: Computer Organization Fall Semester 2001

Final Project: Design of a 32-Bit Computer

Due: Monday, 12/17/01 (demo, presentation, and report)

Purpose:

You and your team are to design a 32-bit computer, as shown in the attached block diagram. The design should be done using Cadence Composer for schematic capture and Verilog/XL for logic simulation. The figure shows a suggested organization for your computer, but may need some additions, modifications, or enhancements, as you see fit, to meet the requirements below.

Requirements to be met:

  1. A global reset line must initialize the circuit to some known state.
  2. Assume that the program stored in memory is always stored at address 0.
  3. All sequential elements in the circuit share the same common clock.
  4. There are eight 32-bit general purpose registers – R0…R7
  5. The computer contains one ALU whose functions you need to select/design.
  6. A shifter (clocked register) with parallel load feature.
  7. Your design contains PC, IR, MAR, MBR, and CAR registers.
  8. The control unit is a microprogrammed, hard-wired CU.
  9. The instruction length is 32 bits with the following suggested fields (5-bit OPCODE, three 3-bit register address operands, and an 18 bit IMMEDIATE operand).
  10. The 15 instruction load/store ISA (given below) is to be implemented with microroutines stored in the control ROM.
  11. The memory is a 256 word x 32 bits/word RAM (provided).
  12. The control ROM (provided) contains 64 words x 32 bits/word. The control word format is to be designed by you.

Deliverables:

  1. List of registers.
  2. Table of instructions.
  3. Table of register micro-operations.
  4. Derivation of all logic circuitry.
  5. All schematics and symbols involved in the design.
  6. A schematic for the entire system.
  7. Micro-program written in English with associated control words.
  8. Demonstration of the working project.
  9. All related simulation files.
  10. A completed report on your computer design containing the above items.

Instruction Set:

Instruction RTL

LD Rx, YRx M[Y]

ST Y, RxM[Y]  Rx

LDI Rx, #NRx #N

XCHRx, RyRx Ry

ADDRx, Ry, RzRx  Ry + Rz

SUBRx, Ry, RzRx  Ry - Rz

MPYRx, Ry, RzRx  Ry x Rz

INCRxRx  Rx + 1

DECRxRx  Rx - 1

SHLRxRx  Rx[30:0]||0

SHRRxRx  0||Rx[31:1]

JMPYPC  Y

BZYIf Z=1, PC  Y; otherwise PC  PC + 1

BNZYIf Z=0, PC  Y; otherwise PC  PC + 1

RETend execution.

Hints:

  • Identify ALU functions.
  • Identify the size of the control word.
  • Define bitmaps for all the fields in your instructions.
  • Define a micro-program structure, i.e. map opcodes to physical addresses in the ROM, register address operands fed to the register stack decoder (for writing) and MUX’s (for reading), and immediate field to register input MUX.
  • You should have as a minimum, an Instruction Fetch micro-routine, an Operand Decode micro-routine, and a micro-routine for every instruction.
  • Dotted lines (in the block diagram) are control lines coming from the CU.

Test Programs:

Program 1)

LDI R0, #N1

LDIR1, #N2

SUBR0, R1

BZZero-result

LDIR7, 12121212\h

JMPDone

Zero-result:LDIR7, A5A5A5A5\h

Done:RET

Program 2)

LDIR0, 12345678\h

LDI R1, 87654321\h

XCHR0, R1

RET

Program 3)

LDIR4, #N1

LDIR5, #N2

MPYR6, R5, R4

STX, R6

LDR7, X

SUBR6, R7

BZCorrect:

LDIR0, FFFFFFFF\h

JMPDone:

Correct:LDIR0, 11111111\h

Done:RET

Program 4)

LDIR1, #N1

LDIR2, #N2

INCR1

DEC R2

ADD R3, R1, R2

SHLR3

DEC R1

SUBR4, R3, R1

BNZDifferent:

LDIR0, 55555555\h

JMPDone:

Different:LDIR0, F0F0F0F0\h

Done:RET

R. W. Knepper

November 14, 2001