Thursday 5th March 09,

Due Date Thursday 12th March 09

Assignment_5

  1. Design a 3 input CMOS static NAND gate for: a) minimum area; b) minimum propagation delay; c) equal rise and fall time; d) determine the worst case rise and fall time if the NAND gate is driving a 0.1 pf load.
  2. Design a gate to implement the function F(A,B,C,D) = (AB + CD)’ in Pseudo NMOS. Analyze the circuit for valid operation at logic high and logic

Use the following SPICE parameters for this assignment.

SPICE Transistor Parameters

Parameter / NMOS / PMOS / Units / Source / Description
VTO
KP
GAMMA
PHI
LAMBDA
RD
RS
CBD
CBS
IS
PB
CGSO
CGDO
CGBO
RSH
CJ
MJ
CJSW
MJSW
JS
TOX
NSUB
NSS
NFS
TPG
XJ
LD
UO
VMAX / 0.7
40E-6
1.1
0.6
0.01
(40)
(40)
0.7
3.0E-10
3.0E-10
5.0E-10
25
4.4E-10
0.5
4.0E-10
0.3
1.0E-5
5.0E-8
1.7E16
0
0
1
6.0E-7
3.5E-7
775
1.0E5 / -0.8
12E-6
0.6
0.6
0.03
(100)
(100)
0.6
2.5E-10
2.5E-10
5.0E-10
80
1.5E-4
0.6
4.0E-10
0.6
1.0E-5
5.0E-8
5.0E15
0
0
1
5.0E-7
2.5E-7
250
0.7E5 / V
(A/V2)
(V0.5)
V
1/V
ohms
ohms
F
F
A
V
F/m
F/m
F/m
Ohms/sq.
(F/m2)
-
F/m
-
(A/m2)
m
(1/cm3)
(1/cm2)
(1/cm2)
-
m
m
(cm2/Vs) / (1)
(5)
(1)
(3)
(5)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(3)
(3)
(1)
(1)
(1)
(1) / -zero bias threshold voltage
-transconductance parameter
-bulk threshold parameter
-surface potential
-channel-length modulation
-drain ohmic resistance (w=6)
-source ohmic resistance()
-zero bias B-D juction cap.
-zero bias B-S juction cap.
-bulk junction sat.current
-bulk junction potential;
-G-S overlap capacitance
-G-D overlap capacitance
-G-bulk overlap capacitance
-diffusion sheet resistance
-zero bias bulk junction cap.
-bulk junction grading coef.
-bulk junction sidewall cap.
-sidewall cap. Grading coef.
-bulk jinction sat.current
-oxide thickness
-substrate doping
-surface state density
-fast surface state density
-type of gate material
-metallurgical junction depth
-lateral diffusion
-surface mobility
-maximum drift velocity m/s

SPICE Level 3 Parameters

Parameter / NMOS / PMOS / Units / Source / Description
THETA
KAPPA
ETA / 0.11
1.0
0.05 / 0.13
1.0
0.3 / 1/V
-
- / (1)
(1)
(1) / -mobility modulation
-saturation field factor
-static feedback

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Other Electrical Parameters

Capacitance
(pF/m2) / Edge Component
(pF/m) / Source
Gate (Cox)
Metal1 – Field
Metal1 – Poly
Metal1 – Diffusion
Poly – Field
Metal2 – Field
Metal2 – Diffusion
Metal2 – Poly
Metal2 – Metal1
Capacitor P + - Poly
(0.1%/V linearity) / 6.9E-4
2.7E-5
5.0E-5
5.0E-5
6.0E-5
1.4E-5
1.6E-5
2.0E-5
2.5E-5
6.9E-4 / 0.5E-4
0.4E-4
0.2E-4
2.0E-5
0.5E-4 / (1)
(1)
(1)
(1)
(1)
(4)
(4)
(4)
(4)
(*)
(1)
Resistance / (ohms/sq.) / Source
N+ Diffusion
P+ Diffusion
N+ Poly
Capacitor P+
P-well
Metal1
Metal2
3  3 metal1 – P + Diffusion Contact
3  3 metal1 – N + Diffusion Contact
3  3 metal1 – N + Poly Contact / 25
80
18
300
4K
0.035
0.030
121
44
25 / (1)
(1)
(5)
(1)
(1)
(4)
(4)
(5)
(5)
(5)

Maximum operating voltage: 5 volts.

Sources: (1) D. Smith of NTE, presented at CMC Workshop June 6-7, 1985.

Page 1 of 2 Assignment #5