PROJECT_Fall_2017
Project description
The goal of this project is to design a multiplier accumulator circuit: in 3 stages:
1)Design an 8 bits register. A 16 bits register and a 25 bitsregister.
8bits of data are arriving on lines A & B in parallel on registers RA and RB. Numbers are unsigned binary numbers. A total of 10 numbers will arrive in succession on each line. Data are loaded into registers RA & RB by the command line LOAD.
2)Design a parallel multiplier
Use the parallel multiplier designed to multiply the multiplier (RA) and the multiplicand (RB). Store theresult in register, RC.
3)Design an Adder.
The Adder is used to add the ten results from the multiplier.
The output result will be in register RD.
You are expected to write the VHDL code, compile it, simulate your VHDL design code, test it, synthesize it technology map it and obtain speed, area and power consumption for each and the overall design.
Figure 1: Multiplier/ Accumulator black box
.1Requirements
Table 1 is a summary of the design requirements. There are certain behaviors on the inputs that were not specified in the COEN 6501 project description and would allow for different interpretation on these signals. Since these behaviors need to be specific in order to have a working multiplier/accumulator, additional requirements were then added (as described in the “Comment” column).
Requirement number / Description / CommentR1 / The design shall perform an 8bits * 8bits multiplication of each pair of the operands(unsigned numbers) and add the results to the accumulator.
R2 / The design shall be structural.
R3 / The operands A and B are latched into registers RA and RB when LOAD transitions from high to low.
R4 / The CLEAR signal will clear all registers to ‘0’.
R5 / The 16-bit multiplication result shall be loaded into the 16-bits RC port.
R6 / The accumulator performs the addition until END_FLAG becomes high (All ten numbers been read).
R7 / The Test Bench,& Stimulator can be constructed using “Algorithmic” modeling method.
Table 1: Design Requirements
Signal Specifications
A0-A7: Unsigned 8 bit Operand A
B0-B7: Unsigned 8 bit Operand B
C0-C15 Unsigned Output
CLR: Clears selected registers
LOAD: Loads Operand into internal register
CLK:Clock input
END_FLAG Indicates end of accumulation
.2Optional
Expansion of the method for16 bits operands.
Pipelining of the design.
Synthesis of the design using FPGA board
.3Delivery:
.4 Project reports due date is 2:00 P.M.Tuesday Dec. 12th,2076 (to be handed to me in my office or to the secretary at front desk).
.5Penalty for late delivery
.6 2 marks for the first day. 1 additional mark for each day after.
.7Evaluation:
a)Give full design particulars and all circuits used.
b) Model your circuit using Structural VHDL
c) Simulate your design with various inputs that tests your circuit effectively
d) Provide detailed timing diagram
e) Give good documentation
f) comment on the design results