Raghunandan. C Ph: +91-9886719120, Bangalore
e-mail:
ObjectiveLooking for challenging assignments in VLSI Physical design domain where I could constantly learn and successfully deliver solutions to problems
Professional Summary§ ~1 year of experience in Physical design field involving RTL to GDSII of a block which is part of multi-GHz x86 processor (with Montalvo Systems)
§ 3 years of experience in Telecom domain (with BSNL)
Project DetailsØ Implementation, Timing closure and Physical Design of Level-3 Cache block in x86 processor working at 1.35 GHz
Specifications / 1.35 GHz after route at 60nm (Fujitsu fab specific) technology nodeRole / Level 3 Cache module ownership from RTL to GDSII
Highlights / · Manual placement for data paths in the design with high area utilization (87%)
· Custom routing (pre-routes) on higher metal layers up to M11 for timing critical data paths
· Met post-route timing goal of 1.35 GHz within schedule
Responsibilities/ Work involved / Synthesis (partly manual net-listing)
Floor plan and Timing closure
Logical Equivalence Check (LEC)
Placement (partly manual), Scan and Clock Tree Synthesis(CTS)
Clock network extraction and SPICE simulations
Hold analysis and fixes with annotated clock delays
Signal routing, timing closure with extracted SPEF
Physical design verification signoff (LVS, DRC)
Various other signoff flows including EM/IR, Crosstalk noise analysis, Slew fixes etc.
Tools used / Magma Blast create and Blast Builder and Calibre xRC/Laker for extraction, physical design verification checks (DRC, LVS)
Team Size / 1
Ø Physical design of peripheral unit (IOW) in x86 processor
Specifications / 800 MHz after post route at 70nm technology nodeRole / Clock tree synthesis to GDS II
Highlights / Clock analysis and skew fixes for multi clock domain design (Grid, cluster and forwarded clocks)
Responsibilities/ Work involved / Clock Tree Synthesis
Clock network extraction and simulations
Signal routing, DRC and LVS
Hold analysis and fixes with annotated clock delays
EM/IR and Crosstalk noise analysis and fixes
Tools used / Magma suite and Calibre xRC/Laker for extraction, physical design verification checks (DRC, LVS)
Team Size / 1
Ø Timing correlation analysis and Custom routing for a sub-chip (L2TwCi) block
Specifications / 1~2.5 GHz after post route at 60nm technology nodeResponsibilities/ Work involved / Timing correlation analysis between placed and routed db
Custom routes (pre-routes)
Team Size / 1
Technical Skills
Ø Tools : Magma Blast Create, Blast Builder, Quartz time, Blast Pro, Calibre xRC,
HSPICE, UltraSim, Cadence VirtusoSpectre, Cadence Conformal LEC
Ø Languages : MTcl, Tcl, Perl, Verilog
Ø Platform : Linux, Windows
Educational QualificationAcademic/Specialization / College/University / Year / Percentage
MS by Research in VLSI / IIIT – Hyderabad / 2005-07 / 9.3 (CGPA)
B.Tech (ECE) / NBKRIST, Sri Venkateswara Univ. / 1998-02 / 88.67
Intermediate (12th), MPC / Govt. Junior College Anantapur / 1995-97 / 84.60
Academic Projects
§ Project title / Delay analysis of tapered interconnect lines with coding and repeater insertion at various technology nodes
Implementation / Delay minimization techniques effectiveness is verified by carrying out delay analysis for VLSI interconnects. SPICE Simulations are performed for delay analysis with proposed encoding technique at various technology nodes (180, 130, 90 and 65nm)
Environment / Cadence Virutuso Spectre SPICE simulator, Magma Suite
§ Project title / A Portable, low cost, Multi-functional Medical Device
Implementation / Design of low-cost handheld multifunctional medical device for telemedicine application. (Part of Microsoft Research Digital Inclusion Projects 2006-07)
Research Topic (MS Thesis)
Crosstalk noise, Delay and Energy minimization in VLSI Interconnects using proposed Bus-encoding schemes and analysis of process variation effects on encoding schemes
Published WorkØ C. Raghunandan, K. S. Sainarayanan, M. B. Srinivas: "Process Variation Aware Bus-coding scheme for Delay Minimization in VLSI Interconnects,"9th International Symposium on Quality Electronic Design (ISQED'08), March 17-19, 2008, San Jose, CA, USA.
Ø C.Raghunandan, K.S.Sainarayanan, M.B.Srinivas: " Bus-encoding Technique to Reduce Delay, Power and Simultaneous Switching Noise (SSN) in RLC VLSI Interconnects," Proc. of the 17th edition of ACM Great Lakes Symposium on VLSI (GLSVLSI-2007) Stresa-Lago Maggiore, Italy March 11-13, 2007. (Full paper, Acceptance rate: 10.5%)
Ø C.Raghunandan, K.S.Sainarayanan, M.B.Srinivas: "Impact of Process Variations on Bus-Encoding Schemes for Delay Minimization in VLSI Interconnects," Proc. of 11th IEEE Workshop on Signal Propagation on Interconnects (SPI) May 13-16, 2007, Genova, Italy.
Ø C.Raghunandan, K.S.Sainarayanan, M.B.Srinivas: "Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN)," IEEE International Symposium on Circuits and Systems (ISCAS’ 07) New Orleans, USA, May 27-30, 2007.
Achievements/RecognitionsØ Outstanding achievement award for team effort and timely delivery of Level-3 cache block for Trial tape-out in semi custom design team
Ø Participated and presented a research paper at ACM Great Lakes Symposium on VLSI (GLSVLSI-07) Conference held in Stresa, Italy during Mar. 11-13, 2007
Ø Full fee waiver for pursuing M.S by Research at IIIT Hyderabad (2005-2007)
Ø Sri Venkateswara University (SVU) 1ST Rank (Gold medal), B.Tech. 1998-2002 batch
Personal StrengthsØ Highly motivated and adaptable.
Ø Rapid at learning things
Ø Hard working and good at team work
Personal Profile27 Y – Male – Single
Passport No: B3306585
ReferencesContact details of the following references will be provided upon request
§ Mr. Shekhar Saha, Semi Custom Design Manager, Montalvo Systems
§ Mr. Vaideeswaran Sethuraman, Semi Custom CAD Lead Engineer, Montalvo Systems
§ Mr. Vikash Singhal, Implementation Lead, Montalvo Systems
§ Dr. MB Srinivas, Associate Professor, IIIT- Hyderabad
Place: Bangalore Raghunandan. C