The University of Arizona
Chemical and Environmental Engineering Department – Seminar
“Semiconductor Die Thinning Challenges”
Jam Sorooshian, Ph.D.,
OTD Die Prep-Thinning Manager
Intel Corporation
Tuesday, March 10, 2015, 3:30 – 4:45 pm
ARCH, Room 103
ABSTRACT
Over the last three decades, semiconductor giants such as Intel have built their manufacturing systems and equipment capability based upon their learnings in order to maintain Moore’s law. As Moore’s law reaches its own definitive plateau, some branches of semiconductor sciences are leading us to stacking fabricated devices on top of, or within, other devices in order to maintain or enhance Moore’s law cadence, or even create new end-user capabilities. With the ever growing popularity of delivering smaller, faster and power efficient connected devices in the last decade, the semiconductor industry as a whole hasnotbegun to realize the challenges that exist with post-fab processing and specifically as it applies to non-memory applications. Since 2013, packaging requirements and novel interconnect bridge designs have driven the logic and SoC industries to meet size dimensions that have been difficult to achieve with existing process capabilities. As thin die processing on logic/bridge chips approaches ever thinner targets, impacts on device performance, die warpage and overall die prep processing yield become of great concern. This talk sets to provide an overview of the challenges set by new 2D/3D chip designs for thinning and die preparation post-fab, industry roadmaps for thinner products and a new perspective on impacts academia could have on these newest challenges.
BIOSKETCH
Jamshid (Jam) Sorooshian is Intel’s Oregon Technology/Development Wafer thinning manager. Jam was raised in Arizona where he also attended undergraduate and graduate school. He earned his PhD from the University of Arizona in 2005 studying the Thermal and Tribological Effects on non-copper film planarization. In his career at Intel, Jam was an intern with the planar material group in 2001 and later in his career supported the transfer of 45 and 32-nm logic technologies to New Mexico and held roles as front end defect reduction and CMP group leaders. Jam has also held the roles of Front End Yield Integration and Defect Reduction manager throughout his 10 year career at Intel. Jam is on Intel's College of Engineering Advisory Board where he leads and teaches advanced courses in planarization, and serves as a lead adjunct faculty with Georgia Tech University for developing and organizing Intel COE’s continued education degree program with Georgia Tech University and the University of Arizona. He has published a book and over 20 papers in the field of planarization.