Lesson-22 Adders
Ripple Carry Adder
The values in Gray (A3A2A1A0, B3B2B1B0 and C0 )are given while in circles (C4C3C2C1 and S3S2S1S0 )are computed. The simplest multibit adder is the Ripple carry adder, shown below. For N-bit adder, it consist N full adder unts connected in series through their carry-in and carry-out ports, Each FA adds three bits Ai, Bi, and Cin to produce two bit ouput Si and Cout bits. Because the carry must propagate (ripple) through all the stages serially, this is the slowest adder architecture. Roughly, the time required by the FA units to compute the carry out bit is two gate delays per FA units, thus total delay in generating the final carry Cout is 2xN (2x number of FA) . On the other hand this is the most economical adder in terms of the silicon area and in term of power consumption.
c
- Carry Ripple Adder using Sequential Statements.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa1_4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
ci : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
co : out STD_LOGIC);
end fa1_4bit;
architecture Behavioral of fa1_4bit is
signal carry : std_logic_vector(4 downto 0);
begin
carry (0) <= ci;
for I in 0 to 3 LOOP
s(i) <= a(i) xor b(i) xor carry(i);
carry (i+1) <= (a(i) and b(i)) or (b(i) and carry(i)) or (carry(i) and a(i));
end LOOP;
co <= carry (4);
end Behavioral;
------
- Carry Ripple counter using structural Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
s : out STD_LOGIC;
co1 : out STD_LOGIC);
end FA1;
architecture Behavioral of FA1 is
begin
s <= a xor b xorci;
co1<= (a and b) or (b and ci) or (ci and a);
end Behavioral;
------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa1_4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
ci : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
co : out STD_LOGIC);
end fa1_4bit;
architecture Behavioral of fa1_4bit is
signal carry : std_logic_vector(4 downto 0);
begin
carry (0) <= ci;
x1: for I in 0 to 3 GENERATE
X2: entity work.FA1 PORT MAP
(a(i), b(i), carry(i), s(i), carry(i+1));
end GENERATE;
co <= carry(4);
end Behavioral;
RTL Synthesis
Simulation:
Fast Adders :
There are many variants of the fast adders these are:
- Manchaster Carry Chain Adders
- Carry Skip Adders
- Carry select Adders
- Carry Look Ahead adders.
Three signals (Generate, propaget and Kill ) are useful in modeling the fast adder such as Carry Look Ahead Adder. These are described below:
- Generate: Must be ‘1’ when a carry-out must be produced regardless of carry-in. For FA units, this should occur when ‘a’ and ‘b’ are both ‘1’. i.e. G=a.b
- Propagate: Must be ‘1’ when a or b is ‘1’, in which case cout = cin, that is, the circuit must allow cin to propagate. Thus P = a xor b
- Kill : Must be ‘1’ whan a carry-out is impossible to occur, regardless of carry-in, that is, when a and b are both ‘0’. Consequently K = a’.b’
From the full-adder implementation, two signal conditions:
generate G and propagate P.
Pi = Ai xor Bi=> Si = Pi xorCi
Gi = Ai.Bi => Ci+1 = Gi + PiCi
In order to reduce the length of the carry chain, Ci is changed to a more global function spanning multiple Cells
C1 = G0+P0C0
C2 = G1+P1C1
= G1+P1(G0+P0C0)
= G1+P1G0+P1P0C0
= G0-2+ P0-2C0
C3 = G2+P2C2
= G2+P2(G1+P1G0+P1P0C0)
= G2+P2G1+P2P1G0+P2P1P0C0
= G0-3+P0-3C0
C4 = G3+P3C3
= G3+P3(G2+P2G1+P2P1G0+P2P1P0C0)
= G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0 = G0-4+P0-4C0
A 4-bit Carry Look Ahead Adder:
As the number of bits increase, realization of the Carry Look Ahead Adder becomes difficult. So a smaller 4-bit Carry Look Ahead Adder is designed, which can be used as a building block for realizing larger size e.g. 16-bit, 32-bit,64-bit Carry Look Ahead Adders by instantiating this component.
Carry Look Ahead Adder design in VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
useieee.std_logic_arith.all;
entitycarry_lookahead_adder is
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : in STD_LOGIC_vector(3 downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
sum : out STD_LOGIC_vector(3 downto 0)
);
endcarry_lookahead_adder;
architecture Behavioral of carry_lookahead_adder is
SIGNAL G, P, c: STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
------Computation of G and P------
G <= a AND b;
P <= a XOR b;
------Computation of carry: ------
c(0) <= cin;
c(1) <= G(0) OR (P(0) AND cin);
c(2) <= G(1) OR (P(1) AND G(0)) OR (P(1) AND P(0) AND cin);
c(3) <= G(2) OR (P(2) AND G(1)) OR (P(2) AND P(1) AND G(0)) OR (P(2) AND P(1) AND P(0) AND cin);
cout <= G(3) OR (P(3) AND G(2)) OR (P(3) AND P(2) AND G(1)) OR (P(3) AND P(2) AND P(1) AND G(0)) OR (P(3) AND P(2) AND P(1) AND P(0) AND cin);
------Computation of sum:------
sum <= P XOR c;
end Behavioral;
------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entitybig_adder is
PORT (
a, b: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cin: IN STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cout: OUT STD_LOGIC
);
endbig_adder;
------
architecture Behavioral of big_adder is
SIGNAL carry: STD_LOGIC_VECTOR(8 DOWNTO 0);
------component declaration------
COMPONENT carry_lookahead_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cin: IN STD_LOGIC;
sum: OUT
STD_LOGIC_VECTOR(3 DOWNTO 0);
cout: OUT STD_LOGIC);
END COMPONENT;
------
begin
carry(0) <= cin;
------generate statement------
gen_adder: FOR i IN 1 TO 8 GENERATE
adder: carry_lookahead_adder PORT MAP
(
a(4*i-1 DOWNTO 4*i-4),
b(4*i-1 DOWNTO 4*i-4),
carry(i-1),
sum(4*i-1 DOWNTO 4*i-4),
carry(i)
);
END GENERATE;
------
cout <= carry(8);
end Behavioral;
------