EEEE381 – Electronics I
Lab #5: Two-Stage CMOS Op-Amp
Overview
In this lab we will expand on the work done in Lab #4, which introduced the actively-loaded differential pair. A second stage that is comprised of an actively-loaded PMOS common-source amplifier will be added to the differential amplifier from Lab #4. The result is a two-stage complementary MOS (CMOS) amplifier, the CMOS designation referring to the fact that both NMOS and PMOS transistors are used.
Theory
A generic multi-stage amplifier having N stages is shown in Figure 1. The individual stages could be MOS- or BJT-based, and they could be single-transistor stages (like common source), compound transistor stages (like a differential amplifier), or a mix of any of the foregoing. A common theory applies for determining the voltage of the overall multi-stage amplifier irrespective of the individual stage types.
Note that stage k has an input resistance, Rin(k). For stages 1, 2, …, k, …, (N–1), the load on stage k is the input resistance of the next stage, Rin(k+1). For stage N, the load is the actual load, shown as RL. The gain through any given stage depends on its load.
Figure 1. Generic multi-stage amplifier
Designating the voltage gain through stage kas , the gain of the overall amplifier is calculated as the product of the individual stage gains:
.(1)
In the event where the signal source vsig itself has some associated resistance Rsig, the overall gain is given by:
,(2)
where the factor that precedes the product of the individual stage gains represents the voltage division that occurs between Rsig and the input resistance of the first stage, Rin(1).
The small-signal output resistance for a MOSFET operating in the saturation region is given by where is a technology-dependent parameter for a given channel length. Note that ro varies inversely with the DC bias current. The value of for each transistor can be determined by measuring the output resistance at a given bias point, as was done in Lab #2.
Channel-length modulation increases the magnitude of the drain current in a MOSFET above its first-order saturation value that is given by
(3)
for an NMOS device. When the effect of channel-length modulation is included, the more accurate calculation of the drain current is given by
,(4)
Pre-Lab
A two-stage CMOS amplifier is shown in Figure 2. The first stage is an actively-loaded differential amplifier comprised of M1–M4. It is biased using the M6 current source. The second stage is a PMOS common-source amplifier (M7). Transistor M8 provides bias current for M7and functions as an active load on M7. The RD7and RD8resistors can be used to center the DC output voltage at 0 V (only one of them is needed; the other one should be 0 — i.e., omitted). (Channel-length modulation would have to be taken into accountif calculating the DC voltage at the output by hand.)
Figure 2. Two-stage CMOS amplifier
Assume the following parameters for the CD4007 devices: Vtn| = 1.4 V, Vtp=-1.6 V,
= 60A/V2,=23A/V2, W for NMOS = 170u, L=10u, W for PMOS = 360u, L=10u,
n=0.01 andp =0.02
Design the two-stage amplifier to meet two specifications:
(1) The overall small-signal gain, |Av| vo / vid 240 V/V (47.6 dB).
(2) The DC output voltage at the node between M7 and M8 = 0 V 0.1 V;
Your calculated value of Rmust be rounded to a standard 10% resistor value, then the actual small-signal gain must be re-calculated. Set RD7 = RD8 = 0 Ω in your initial design.
***** There is not a unique design solution *****
(continued)
Calculate the minimum value of Vcom(a DC value) that is needed to ensure proper operation of the differential amplifier (i.e., all transistors in saturation). (Since the lower power supply is –5 V, it is possible that Vcom could be negative.)
Simulate the circuit and compare the simulation results to your hand calculations. Explain any discrepancies, re-design if necessary, and adjust RD7orRD8 to center yourDC output voltage to 0 V. Use standard 10% values for RD7 or RD8.
Calculate the output resistance of M8 (Rout8) and the output resistance Rout of the overall amplifier.
Lab Exercise
Using three CD4007 packages, build the circuit in Figure 3. (The pin diagram for the CD4007 packageis shown in Figure 4.) Measure the “10 ” resistoryourself and record the actual resistance prior to inserting it in the circuit. The 51 Ω resistance (shown as a standard 5% resistor value) can be implemented as two 100 Ω resistors in parallel. The 51 Ω /1kΩ voltage divider provides a controllably small vid in order that the voltage swing at the output vo is still in the linear range of amplification — i.e., to ensure that none of the MOSFETs are driven out of saturation.
Figure 3. Two-stage CMOS amplifier with scaled signal generator differential input.
Note that all NMOS body connections (pin 7) go to the lowest supply (–VSS). Since we are using a separate chip for M1andM2from the one for M5andM6, we could eliminate body effect in M1and M2by connecting their bodies directly to their sources. However, that is not realistic because all the NMOS bodies are common in an integrated circuit, tied to the lowest potential in the circuit (not always true). (Also, all the PMOS substrates (bodies) are common, tied to the highest potential in the circuit.) The substrate (pin 14) of the PMOS devicemust be connected to the most positive supply voltage (VDD).
Apply power to VDD before connecting the input signal. Remove the input signal before disconnecting power. Make sure you are grounded before touching the pins of the CD4007MOSFET package.
1)Verify that theM6current source is sinking approximately the designed amount of current from the differential amplifier. This can most easily be accomplished by measuring the voltage drop across the “10 ” resistor and dividing by the actual measured resistance that you recorded earlier while building the circuit.
2)A small-signal differential input must be applied. Note that the signal generator connection in Figure 3 is superimposed on the DC common mode voltage supply Vcom(use the power supply’svariable +6V output for Vcom). Set Vcom = 0 V initially. It will be adjusted in step (3) below.The outputvsigfrom the signal generator has been scaled so that the input to the differential amplifier can be adjusted to about vid=5mV. Set the signal generatorvsigto a sine wave of 1 kHz frequency and 100mV amplitude. Make sure that the signal generator is in “High–Z” mode.
3)Acommon-mode DC supply must be provided in addition to the differential signal to bias the amplifier in the linear operating region (all transistors in saturation). Place a scope on the output signal node (vo)and carefully adjust the VcomDC supply from zero volts until you see an undistorted sine wave on the display. Compare this value of Vcomto the value calculated in your pre-lab preparations.
Caution: You must get Vcomup to a point where the transistors are operating properly — i.e., in saturation. It is not sufficient to merely get a response at the output node. (You will get a response as soon as there is some current flowing. You will also see amplification of the differential input signal, albeit distorted.) You must get Vcom up the point where your current source is operating properly — i.e., at the designed current level. All your results will be invalid if this is not done properly. If Vcom is too low, M6 will not be in saturation. You must monitor the current in M6 and verify that you are getting the desired current.
(continued)
4)Measure the DC output voltage at the node betweenM7 and M8. Add RD7ORRD8 (not both) to adjust it to 0 V 0.1 V.
5)Measure the differential mode voltage gain of the amplifier in Figure 3for an input signal of vid = 5mV at 1 kHz.
N.B.: The two-stage CMOS amplifier of Figures 2 and 3 will be used in Lab #6, so you may wish to keep it assembled once you have it working properly.
Summary and Discussion
Summary of questions to be addressed:
•Is the value of Vcomobtained in part (3) of the lab exerciseconsistent with the value you calculated in your pre-lab preparations?
•What is the differential-mode voltage gain at 1 kHz? Is it consistent with your pre-lab calculations?
•What discrepancies have you noted in your lab measurements compared to your calculated values? How can you account for any observed differences?
Appendix A — PSPICE Instructions
Please refer to the following for assistance in modifying the MbreakN MOSFET model. You also need to modify the MbreakP model similarly see the spice model above for values for W, L, NRD, and NRS.
We want to place the MbreakN Schematic symbol on our schematic then edit and display the properties to represent the CD4007 transistors. We also want to change the name of the spice Model from MbreakN to RIT4007N7.
Finally, we want to let PSPICE know where to find the text
file that has the SPICE MODEL in it. That is done by editing
the PSPICE simulation profile. Under the Configuration
Files Tab, select Include, and then Browse to the Location of
the file where the SPICE model is. (Note: you should have
already placed the text file that has the RIT4007N7 SPICE
model in it on your computer in some location)
Appendix A — SPICE Instructions
Please refer to the following for assistance in modifying the MbreakN MOSFET so that it represents the NMOS FETs in the CD4007 chip.
We want to place the MbreakN Schematic symbol on our schematic then edit and display the properties to represent the CD4007 transistors. We also want to change the name of the spice Model from MbreakN to RIT4007N7.
Finally, we want to let SPICE know where to find the text
file that has the SPICE MODEL in it. That is done by editing
the SPICE simulation profile. Under the Configuration
Files Tab, select Include, and then Browse to the Location of
the file where the SPICE model is. (Note: you should have
already placed the text file that has the RIT4007N7 SPICE
model in it on your computer in some location)
These are two of the several SPICE models in the text file “RIT_SPICE_Models.txt” provided on the lab webpage. You should download the entire text file and place it on your computer. You can include all the models by telling SPICE the location of the downloaded file as shown on the page above (page 8). SPICE will actually only use the models called for by the devices in your schematic.
Check-Off Sheet
A. Pre-Lab
Design of the two-stage amplifier to achieve small-signal voltage gain and DC output voltage specifications: determination of R, RD7, and RD8.
Calculation of output resistances of M8and the overall amplifier.
Calculation of the minimum acceptable value of Vcom.
PSPICE simulation of the overall amplifier; comparison to hand calculations.
B. Experimental
Two-stage amplifier built and tested: verification of designed current amount in current source; determination of Vcom level needed for proper operation; measurement of differential-mode gain.
TA Signature: ______Date: ______
Electronics I – EEEE381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 2017Page 1 of 11
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