Interface Selection Process

Interface Selection Process

Interface / Speed per Channel / Length (m) / Input Format / Output Format / Bi-Directional / Applicable
LVDS Ser/Des / 500Mbps / 10m / LVDS / LVDS / Yes, I2C / Yes
HD/SDI / 1.5Gbps / 200+ m / SDO/SDI / HD-SDI/SDO / No
FPGA-Link / 3.12 Gbps / 20 m / LVDS / CML / No / No
USB 3.0 / 5 Gbps / 3+ m / No
Channel Link III SERDES DS92LX / 1 Gbps / 10m STP / LVCMOS / CML / Yes, I2C / Yes
FPD-Link III SERDES / 2550 Mbps / 10m STP / LVDS / Yes, I2C / No
Camera Link HS / 2.1 Gbps per Cable -8 Supported / 15m to 300m (copper or fiber optic) / 10GBASE-X / 10GBASE-X / Yes / Yes
Gigabit Transceiver TLK2711A / 2 to 2.5 Gbps / 100+ m / VML, TTL / Yes / Yes
Coax Express / 3.125 Gbps / 30+ m / Possibly

Trade and Analysis

LVDS:

-LVDS is adifferential signalingsystem, meaning that it transmits information as the difference between the voltages on a pair of wires; the two wire voltages are compared at the receiver. In a typical implementation, the transmitter injects a constant current of 3.5mAinto the wires, with the direction of current determining the digital logic level. The current passes through a termination resistor of about 100 to 120 ohms (matched to the cable’scharacteristic impedanceto reduce reflections) at the receiving end, and then returns in the opposite direction via the other wire.

-The paired wires reduce electromagnetic noise by creating equal and opposite electromagnetic fields that tend to cancel each other. In addition, the tightly coupled transmission wires will reduce susceptibility to electromagnetic noise interference because the noise will equally affect each wire and appear as a common-mode noise.

-The LVDS receiver is unaffected by common mode noise because it senses the differential voltage, which is not affected by common mode voltage changes.

To apply LVDS to our particular application a repeater /translator IC might be needed to drive the signal 10m+. When researching the protocol it was seen that attenuation greatly affected the differential signal over the 10m cable and signal integrity might be compromised. This in theory could be avoided with the repeater translator IC but hardware tests will likely be used to confirm this.

Links:

USB 3.0 Transceiver

-Supports 3+ Meters of 3.0 Cable Length

-Single 5.0 Gbps UBS 3.0 Physical Layer Transceiver

-Fully Compliant with UBS 3.0 Specification, revision 1.0

-Provides 3.3, 1.8, and 1.1 Supply voltages

-JTAG Support

The USB standard does not require a clock signal to be transmitted across it because it uses a single 40 MHz reference clock that comes from the Crystal. The major problem with USB is that it takes in 16 bit parallel lines and the output of the image sensor is not in that format. It would require and FPGA between the USB transceiver and the image sensor. If the FPGA was not required this would be one of the best options. The internal block diagram for the transceiver is below:

Coax Express:

• CoaXPress is a point to point scalable interface connecting a camera to a frame grabber using 75Ω coaxial cable.
• Became a public royalty-free world standard in March 2011

• High Speed Downlink – carries video data, triggers, GPIO and register control signals. All data is formatted and transferred by means of packets, and the link uses industry standard 8B/10B coding.
• Low Speed Uplink – runs at a fixed rate of 20.833 Mbps, and also uses 8B/10B coding. It carries triggers, GPIO and register control signals. High Speed Uplink is under development using additional coaxial cable.
• Power over CoaXPress (PoCXP) – Power over cable supported. Available power per cable is 13 Watts at the camera.
• Links:

The CoaXPress standard is still a fairly new technology and the implementation is not well-matured. The layout of the power supply unit might compromise the size constraint requirement, so these factors would make it a difficult choice for this project.

-Can support 1 to 8 cable connections

-Each cable can support 15 data lines

-Reliable standard with years of testing and use

-Both standard and mini connectors

-32 GPIOs

-7 Different pulse modes of operation

-Supports fiber optic module for high transfer speed at distances at 300 meters

The major problem with CameraLink is size and its connectors. A CameraLink chip requires a large portion of the space requirement. Because there are 15 data lines in the connectors are large and they are not yet ruggedized to me the IP67 rating. Because the cables have so many data lines the number of differential pairs required is large making the cables very expensive to meet the minimum length of 3 meters.

Channel Link III

-Bi-directional control interface channel with I2C support

-LOCK output reporting pin to ensure link status

-EMI/EMC mitigation

-Embedded clock with DC balanced coding to support AC-coupled interconnects

-6 Programmable GPIO’s

-AT-SPEED BIST

-Can drive cable up to 10 meters, shielded twisted pairs

-Single 1.8V power supply

This standard it good in theory, but in the end it is too slow. It has a 1 Gbps maximum speed of Channel Link III is just too slow to be able to transmit the amount of data we need to transmit. Also, not all the imagers support parallel data output meaning some sort of interface would needed between the image sensor and this interface chip for all the image sensors to be supported.

-Specification managed by the Automated Imaging Association (AIA)

-Protocol implemented over Ethernet/IP/UDP with data transfer rates up to 1 Gbps using Gbps Ethernet, scalable to 10 Gbps with 10-Gbps Ethernet

-Data transfer length up to 100 m with copper

-Use of switches, repeaters, or fiber optic converters to increase the data transfer length

-Use of low-cost cables (CAT5e or CAT6), standard connectors, and hardware

You can obtain several key benefits by implementing GigE Vision applications using FPGAs such as Altera’sCyclone®III and Cyclone IV device families:

-Integration of image capture, camera interfaces, preprocessing, and communications within a single FPGA device

-Flexibility to support different camera interfaces and bus interfaces as they evolve

-Lower total cost of ownership (TCO) with reduced board size, reduced component count, and minimal hardware re-spins

-Reduced risk of obsolescence due to long FPGA life cycles and easy migration to newer FPGA families

Link: