Srinilayam • 25-10-12 • Fire Station Street • NR Pet • Eluru -534006
Phone:+91 9885838554 • E-mail:
Objective
Being a final year post graduation student in the VLSI stream, I am seeking for the position of a Design Engineer that requires applying my analytical skills in the field of VLSI.
Education
- Now pursuingM.Tech program specialized inVLSI &Embedded Systems in IIIT, Hyderabadobtained 6.2 CGPA till now.
- In 2006received B.Edegree in the field ofElectronicsCommunications Engineeringfrom Sir C R Reddy COE, Eluru (Affiliated to AndhraUniversity) with69%.
- In 2002 completed Intermediate (MPC)in Siddartha Vidyalaya, Eluru with 93%.
- In 2000 finished SSC in SriHelapuriHigh School, Eluru with 79%.
Subjects Learned
Analog, Mixed Signal and Low -Power Design, VLSI Algorithms, Advanced Digital Design with HDLs, Formal Foundations of VLSI Design, and Introduction to VLSI Design.
Computer Courses
Certified as EXCELLENT in “Honors diploma in Web Applications”, in which Linux, SQL, Software Engineering etc. are the part of its curriculum at NIIT, ELURU inMarch 2006.
Project works
Data Compression using LZW algorithm with C: Our project implements the LZ algorithm in an efficient way and uses Gzip, Deflate standards for compressed data. So, any commercial software like WinZip can decompress the file, which is compressed using these standards.
Data Security with Steganography using MATLAB: Our project consists of two phases: The first phase is data encryption and the second phase is hiding encrypted data in the picture. As an application to this project Digital watermarking was implemented.
Hardware implementation of AES in Puzzle Algorithm: In this project we Implemented a novel video encryption algorithm, called Puzzle, to encrypt video data. It is fast enough to meet real-time demands and provides a sufficient security. The algorithm can readily be incorporated into existing multimedia systems.
ACHIEVEMENTS
- Runner-upin the Poster Presentation contest at NIT Warangal in TechnoZion 06, a National Level Technical Symposium.
- Won Second Prize in paper presentation contest in National level Technical Symposium –Knew 06, Channabasaveswara Institute of Technology, Tumkur, Karnataka.
- Stood in Third Position in National Level Paper Presentation Contest at JNTU,Kakinada in AEON 05.
- Got Consolation Prize in National Level Paper Presentation Contest at AudisankaraCollege of Engineering & Technology, Gudur in FLAIR 05.
EDA Tools (Digital design)
Simulation: Active HDL
Synthesis : QUARTUS II (Altera)
FPGA implementation tools : Quartus-II (Altera)
EDA Tools (ANLOG design)
Tanner EDA tools
schematic Capture: S-Edit
Simulation: T-Spice, W-Edit
Physical Layout: L-Edit
Verification: L-Edit Standard DRC, L-Edit LVS
Technical Skills
Programming languages: C, shell, perl, SQL, HTML, PhP, XML, C++, java
HDLs : Verilog
Operating Systems : Linux, Windows
STRENGTHs
Good Knowledge in the VLSI Design flow.
Strong analytical Ability Skills.
Excellent English Communication skills both written and verbal.
Basic Knowledge of Networking and Hardware.
Interests and activities
Class representative &Lab in-charge for PG2k6 VLSI batch in IIIT.
Active member of Student Parliament in IIIT –H.
Led the IETE Student Forum in SirCRREngineeringCollege, Eluru as the President in B.E final year.
Community activities
Member of Ashakiran health wing in IIIT –H
Active Member of NSS in Sir CRR Engineering college, Eluru
References:
Available on request.