@head: Max's Chips and Dips: Magma's Automated Chip Creation now Package-Aware

@deck:It doesn’t take a genius to realize that combining an automated chip creation environment like Talus with a tool like RioMagic that works on the chip and the package designs concurrently has to be a jolly good idea.

@text: Eeeek! DAC 2006 is almost upon us. I'm not ready. I'd better start packing. One of the great things about being a writer / editor is that one gets to hear about all sorts of cool stuff long before it's public knowledge. The downside, of course, is that you can't tell anyone about it, which can be more than a little frustrating, let me tell you!

But now we're starting to see the first waves of pre-DAC announcements that are (I have no doubt) intended to tempt us to visit their respective owner's booths at the show to learn more. (They need not have bothered, because I'll be there anyway asking all sorts of probing questions.)

Just a few moments ago as I pen these words, for example, Rio Design Automation and Magma Design Automation announced that Rio's RioMagic package-aware chip design software has been integrated with Magma's Talus Automated Chip Creation solution.

What does all of this mean? Well, let's first remind ourselves as to what the two players are up to on their own.

Rio Design and RioMagic

Traditionally, the guys and gals designing a silicon chip and the folks designing the package for that chip have not spent much time chatting and communicating with each other. The end result is that when making I/O placement decisions and bump assignments by hand, the chip design team can end up (a) with a significantly larger die area than they really need and (b) with something that is going to be a swine for the packaging folks to work with.

Less than optimal placements and assignments on the die may force the package designers to use a more expensive package with more layers, and they may also run into a variety of power integrity and signal integrity issues.

This is the point where RioMagic leaps onto the center of the stage and thrusts itself into the limelight. (As an aside, the term "limelight" comes from the incandescent light produced by a rod of lime bathed in a flame of oxygen and hydrogen. At the time it was invented, limelight was the brightest source of artificial light known. One of its first uses was for lighting theater stages, and actors and actresses were keen to position themselves "in the limelight" so as to be seen to their best effect. But we digress . . .)

RioMagic sits directly between your existing chip design and package design tools and works on the chip and the package designs concurrently. For example, RioMagic concurrently performs I/O placement and bump assignment on the chip – and escape analysis and escape routing on the package. As part of this process, RioMagic continuously explores different design scenarios while simultaneously analyzing the power integrity and signal integrity impacts of any of its design decisions.

The result from the chip side of the fence is optimal die size and optimal bump pitch and optimal bump assignment to match the package. The result from the package side of the fence is to use the cheapest package with the smallest number of layers and to make all of the assignments in such a way as to minimize any power integrity and signal integrity issues. Cool!

Magma and Talus

Now let's turn our attention to those little rapscallions at Magma, who recently announced their Talus automated chip creation (ACC) system. In a nutshell, Talus accepts as input the design RTL and performs the following tasks:

<ul>

<li>Automated RTL synthesis, DFT synthesis, and physical synthesis.</li>

<li>Automated logical-to-physical partitioning, block-shaping, and floorplanning.</li>

<li>Automated clock-tree synthesis.</li>

<li>Automated power grid design.</li>

<li>Automated signal integrity (SI)-driven routing.</li>

</ul>

That is, you give Talus your RTL and constraints, and it gives you back a complete chip design. Using parallelized and distributed concurrent processing technology to automatically partition physical implementation tasks across multiple processors means a complete RTL-to-GDSII pass (including synthesis, floorplanning, clock-tree synthesis, power grid design, and detailed routing) can be performed in only two days, irrespective of the size of the design. Mega Cool!

Talus and RioMagic

Well, it doesn’t take a genius to realize that combining an automated chip creation environment like Talus with a tool like RioMagic that works on the chip and the package designs concurrently has to be a jolly good idea. I can’t wait to see all of this in action, so both Rio and Magma can expect to see me leaping into their booths at DAC asking questions with gusto and abandon (you have been warned &ndash, be afraid, be very afraid). Until next time, have a good one!

Rio Design Automation’s RioMagic and Magma’s New Talus

Reach Higher Level of Interoperability

Tight Integration Between Tools Ensures Package-Aware

Chip Design from RTL-to-GDSII

SANTA CLARA, Calif., July 13, 2006  Rio Design Automation Inc. today said its RioMagic package-aware chip design software has been integrated with Magma Design Automation’s Talus™, an integrated circuit (IC) implementation product, extending Talus’ RTL-to-GDSII capabilities to include package prototyping.

This integration offers design teams a way to consistently convey chip information to the package engineer under one uniform design environment. It lets designers compare bump mismatches with a new package or floorplan design and to investigate die size/package cost tradeoffs.

Kam Kittrell, general manager of Magma’s Design Implementation Business Unit, said, “A true chip/package co-design flow can only be achieved when there is a tight integration between design domains. Talus’ automated floorplanning combined with RioMagic’s automated package-aware I/O site planning is unmatched in the industry for performance and optimal die size.”

“The combination of RioMagic and Talus strengthens Talus’ automation and extends it into package design to address a complete design problem,” said Kaushik Sheth, Rio Design Automation’s chief executive officer. “Additionally, development time is reduced from three weeks to two days.”

RioMagic, introduced earlier this year, bridges the gap between the design of high-performance ICs, their packages and the rest of the system. Talus’ advanced implementation capabilities are designed to reduce the design development cycle and design costs and speed yield ramp-up for ICs targeted at 65-nanometer (nm) and smaller process geometries.

RioMagic enables chip/package I/O planning and optimization through a single data model. This unified data model facilitates the optimization process by bringing all design elements into the synthesis flow for the entire chip and package to be represented simultaneously.

About Rio Design Automation

Rio Design Automation is an electronic design automation (EDA) company bridging the gap between the design of high-performance integrated circuits (ICs) and packages, and a chip’s integration with the rest of the electronic system. Its revolutionary approach offers chip designers package-aware software to that enables I/O optimization tradeoffs to take place in the context of the package and the printed circuit board (PCB). Corporate headquarters is located at: 2901 Tasman Drive, Suite 112, Santa Clara, Calif. 95054. Telephone: (408) 844-8038. Facsimile: (408) 844-8945. Email: . Website: