VERILOG HDL MODELING
1. Objective(s):
The activity aims to let the students create a Verilog code indifferent level of abstractions. It also aims to let the students realize combinational circuits in HDL.
2. Intended Learning Outcomes (ILOs):
The students shall be able to:
1. Create a Verilog code using different modeling.
2. Simulate the operation of combinational circuit using Verilog.
3. Create appropriate Test Bench for each Verilog code.
3. Discussion:
Modeling Styles
- Gate – level modeling – using instantiations of predefined and user – defined primitive gates.
- Dataflow modeling – using continuous assignment statements with keyword assign.
- Behavioral modeling – using procedural assignment statements with the keyword always.
Another group of primitives are three-state (tri-state is also used to refer to these structures) gates. These primitives are bufif1, notif1, bufif0, and notif0.
Also we have another group which are NMOS, PMOS and CMOS structures. These are switches that are used in switch level description of gates, complex gates, and busses. The nmos (pmos) primitive is a simple switch with an active high (low) control input. The cmos switch is usually used with two complementary control inputs. These switches behave like the three state gates. They are different in their output voltage levels and drive strengths.
Data – Flow Modeling. It is the level of abstraction in Verilog using continuous assignment statements with keyword assign. At a higher level than gates and transistors, a combinational circuit may be in data – flow modeling by describing the Boolean, logical, and arithmetic expressions. For this purpose the Verilog concurrent assign statement is used. Effectively, this assign statement is like driving output with the inputs. The difference is that, the use of an assign statement gives us more flexibility and allows the use of more complex functions than what is available as primitive gates. Instead of being limited to the gates in gate – level modeling.
Behavioral Modeling. It is the level of abstraction in Verilog using always or initial block. It describes the functionality of a system. It is also described by specifying a set of concurrent active procedural block. A module may contain multiple always statements and multiple initial statements. Each statement starts a separate control flow and starts execution at time 0.
An initial statement executes only once and begins its execution at start of simulation which is at time 0.
Syntax :initial
[timing_control] procedural_statement
An always statement executesrepeatedly and also begins its execution at start of simulation which is at time 0.
Syntax :always
[timing_control] procedural_statement
A block statement provides a mechanism to group two or more statements to act syntactically like a single statement. There are two kinds of blocks in Verilog HDL. These are :
◦Sequential block ( begin…end ) : Statements are executed sequentially in the given order.
◦Parallel block ( fork … join ) : Statements in this block execute concurrently.
4. Resources:
Computers with Verilog Simulator
5. Procedure:
4 – 1 Multiplexer (Gate Level)
- Using notepad, write the following code for the figure below:
module Mux4_1(x,y,a,b,c,d,m);
input x,y,a,b,c,d;
output m;
not n1(net1,x);
not n2(net2,y);
and a1(net3,net1,net2,d);
and a2(net4,net1,y,c);
and a3(net5,x,net2,b);
and a4(net6,x,y,a);
or o1(m,net3,net4,net5,net6);
endmodule
module TestBench;
reg x,y,a,b,c,d;
wire m;
initial
begin
$display("x y d c b a m");
a = 1'b0; b = 1'b0; c = 1'b0; d = 1'b0; x = 1'b0; y = 1'b0;
#64 $finish;
end
always #32 x = ~x;
always #16 y = ~y;
always #8 a = ~a;
always #4 b = ~b;
always #2 c = ~c;
always #1 d = ~d;
Mux4_1 U1(x,y,a,b,c,d,m);
initial
$monitor("%b %b %b %b %b %b %b",x,y,a,b,c,d,m);
endmodule
- Save the code with MUX4_1 as filenamein desktop and convert it to a v filewith MUX4_1.v as file name.
- Save a copy of MUX4_1.v file to the bin of iverilog folder in drive C.
- Using the CMD compile your code. Make sure to enter in bin iverilog before compiling it. Type cd c:\iverilog\bin and hit enter key.
- Type iverilog –o mux4_1 MUX4_1.v If there’s no error message displayed in the screen that means your code is compiled correctly.
- Type vvp mux4_1 . What happened? ______
2 – 4 DECODER (Register Transfer Level)
- Using notepad, write the following code for the figure below:
2-4 Decoder
module Dec_2_4(A0,A1,D0,D1,D2,D3);
input A0,A1;
output D0,D1,D2,D3;
assign {D3, D2, D1, D0} =
( {A0, A1} == 2'b00 ) ? 4'b0001 :
( {A0, A1} == 2'b01 ) ? 4'b0010 :
( {A0, A1} == 2'b10 ) ? 4'b0100 :
( {A0, A1} == 2'b11 ) ? 4'b1000 :
4'b0000;
endmodule
module TestBench;
reg A0,A1;
wire D0,D1,D2,D3;
initial
begin
$display("A0 A1 D3 D2 D1 D0");
A0 = 1'b0; A1 = 1'b0;
#4 $finish;
end
always #2 A0 = ~A0;
always #1 A1 = ~A1;
Dec_2_4 U1(A0,A1,D0,D1,D2,D3);
initial
$monitor("%b %b %b %b %b %b",A0,A1,D3,D2,D1,D0);
endmodule
- Save the code with DEC2_4 as filenamein desktop and convert it to a v filewith DEC2_4.v as file name.
- Save a copy of DEC2_4.v file to the bin of iverilog folder in drive C.
- Using the CMD compile your code. Make sure to enter in bin iverilog before compiling it. Type cd c:\iverilog\bin and hit enter key.
- Type iverilog –o dec2_4 DEC2_4.v If there’s no error message displayed in the screen that means your code is compiled correctly.
- Type vvp dec2_4 . What happened? ______
FULL ADDER (Behavioral Level)
- Using notepad, write the following code for the figure below:
Full Adder
module fulladder(a,b,c, sum, carry);
input a,b,c;
output sum,carry;
reg sum,carry;
always @(a or b or c)
begin
case ({a,b,c})
3'b000:begin
sum = 1'b0;
carry = 1'b0;
end
3'b001:begin
sum = 1'b1;
carry = 1'b0;
end
3'b010:begin
sum = 1'b1;
carry = 1'b0;
end
3'b011:begin
sum = 1'b0;
carry = 1'b1;
end
3'b100:begin
sum = 1'b1;
carry = 1'b0;
end
3'b101:begin
sum = 1'b0;
carry = 1'b1;
end
3'b110:begin
sum = 1'b0;
carry = 1'b1;
end
3'b111:begin
sum = 1'b1;
carry = 1'b1;
end
default: begin
sum = 1'b0;
carry = 1'b0;
end
endcase
end
endmodule
module TestBench;
reg a,b,c;
wire sum,carry;
initial
begin
$display(" a b c sum carry");
a = 1'b0; b = 1'b0; c = 1'b0;
#8 $finish;
end
always #4 a = ~a;
always #2 b = ~b;
always #1 c = ~c;
fulladder U1(a,b,c, sum, carry);
initial
$monitor(" %b %b %b %b %b",a,b,c,sum,carry);
endmodule
- Save the code with FULL_ADDER as filename in desktop and convert it to a v filewith FULL_ADDER.v as file name.
- Save a copy of FULL_ADDER.v file to the bin of iverilog folder in drive C.
- Using the CMD compile your code. Make sure to enter in bin iverilog before compiling it. Type cd c:\iverilog\bin and hit enter key.
- Type iverilog –o fulladderFULL_ADDER.v If there’s no error message displayed in the screen that means your code is compiled correctly.
- Type vvpfulladder . What happened? ______
Course: / Experiment No.:
Group No.: / Section:
Group Members: / Date Performed:
Date Submitted:
Instructor:
6. Data and Results:
DATA AND RESULT:
x / y / a / b / c / d / m
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Table 2.1 4-1 Multiplexer
A0 / A1 / D3 / D2 / D1 / D0
Table 2.2 2-4 Decoder
a / b / c / Sum / Carry
Table 2.3 3-Bit Full Adder
Supplemental Activity :
- Create a Verilog code with test bench for the following:
b. 1 – 4 Demultiplexer – Gate Level
c. 8 – 3 Encoder – Register Transfer Level
d. 3 – 8 Decoder – Register Transfer Level
e. Half – Adder –Behavioral Level
f. Full Subtracter – Behavioral Level
g. 3-bit Comparator – (Gate Level, Register Transfer Level and Behavioral Level)
7. Conclusion:
______
8. Assessment (Rubric for Laboratory Performance):
AREA / BEGINNER
1 / AVERAGE
2 / EXPERT
3 / EXEMPLARY
4 / RATING
- Manipulative Skills
- Presentation
- Documentation
- Time Management
- Neatness
- Completeness
TOTAL SCORE
Computation =
Evaluated By:Date: