README

v7.1 DSP Design Flow Workshop

Digilent Spartan-3

COURSE DESCRIPTION

The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification.

PREREQUISITES

·  Fundamentals of MATLAB/Simulink and Xilinx FPGAs

·  Basics of digital signal processing theory for functions such as FIR (Finite Impulse Response) filters

WORKSHOP GOALS

·  Learn how to implement a DSP design without having to be an FPGA expert

·  Become comfortable using System Generator to develop lectures & labs, or implement research projects.

SKILLS GAINED

·  Understand the strengths and weaknesses of three design flows (HDL, CORE Generator, System Generator)

·  Make a decision regarding which design flow is more appropriate based on needs and FPGA expertise

·  Understand the impact of some decisions made in the Simulink environment based on the resulting size of the FPGA design

·  Debug and optimize a design in the Simulink environment

REQUIREMENTS

The workshop has been tested on a PC running the Windows XP Professional operating system.

Software / Additional System Requirements
V7.1 System Generator for DSP
V7.1i ISE Foundation Software + SP1
V7.1 Chipscope-Pro / ·  512 MB of memory
·  Java run-time environment version 1.5.0-b.64 (automatically included in chipscope-pro software installation)
Mathworks release R13.1 or R14 (includes Matlab/simulink) + Signal Processing blockset
Hardware / Additional System Requirements
Digilent Spartan-3 starter kit (includes power supply and download cable) / Parallel printer port on PC (for connecting the download cable)

COURSE OUTLINE

Day 1 Agenda / Day 1 Materials
Introduction / 01intro.ppt
DSP Design Flows in FPGA / 02flows.ppt
Lab 1: Creating a 12x8 MAC using VHDL and Core Generator / 11lab01.doc (lab 1 instructions)
/labs/lab1 (lab 1 “user” directory)
/labsolutions/lab1 (lab 1 solutions)
Lab 2: Creating a 12x8 MAC using System Generator for DSP / 12lab02.doc (lab 2 instructions)
/labs/lab2 (lab 2 “user” directory)
/labsolutions/lab1 (lab 1 solutions)
Digital Filters / 03filters.ppt
Lab 3: Designing an FIR filter / 13lab03.doc (lab 3 instructions)
Day 2 Agenda / Day 2 Materials
Looking under the hood / 04hood.ppt
Lab 4: Looking under the hood / 14lab04.doc (lab 4 instructions)
Controlling the system / 05control.ppt
Lab 5: Controlling the system / 15lab05.doc (lab 5 instructions)
Multi-rate systems / 06multirate.ppt
Lab 6: Designing a MAC FIR / 16lab06.doc (lab 6 instructions)

LAB DESCRIPTION

Lab 1: Create a 12 X 8 multiply-accumulate (MAC) function using a combination of VHDL and Core Generator

Lab 2 : Brief introduction to Simulink; Overview of quantization and overflow; Create the same 12 X 8 MAC using System Generator for DSP

Lab 3: Use the FDA Tool to generate coefficients for a low-pass filter; implement low-pass filter using DA FIR filter block from System Generator; simulate with white noise and test in hardware via JTAG co-simulation

Lab 4: Observe the effects in hardware when changing quantization and overflow parameters

Lab 5: Create an address generator using 1) basic System Generator blocks, and 2) m-code block

Lab 6: Using the design in lab 5, you will create a 92-tap MAC based FIR filter; you will simulate the filter with white noise and verify in hardware via JTAG co-simulation

DIRECTORY STRUCTURE

Description / Directory
Lecture Slides / C:/xup/dsp_flow/slides/ (.ppt files listed in course outline)
Lab Exercises / C:/xup/dsp_flow/lab_docs/ (.word docs listed in course outline)
“user” directories / C:/xup/dsp_flow/labs/(lab1, lab2, lab3, lab4, lab5, lab6)
Lab solutions / C:/xup/dsp_flow/labsolutions/(lab1, lab2, lab3, lab4, lab5, lab6)
Board Support Files / C:/xup/dsp_flow/digilentJTAGfiles/ (files required for JTAG cosim support)

DIGILENT SPARTAN-3 BOARD SUPPORT

To enable hardware-in-the-loop support via JTAG co-simulation with the Digilent Spartan-3 board, unzip the spartan3.zip file in the System Generator for DSP install path as follows

C:\MATLAB701\toolbox\xilinx\sysgen\plugins\compilation\Hardware Co-Simulation\

So that the following sub-directory is created

C:\MATLAB701\toolbox\xilinx\sysgen\plugins\compilation\Hardware Co-Simulation\Digilent\Spartan-3

And the following files appear in this new subdirectory:

·  Spartan_3.ucf

·  Spartan_3.xml

·  Spartan_3_libgen.m

·  Spartan_3_postgeneration.m

·  Spartan_3_target.m

·  Xltarget.m