Serial ATA CRC Error Reporting

e01133r0

e05133r10

Serial ATA ICRC Reporting

To:T13 Technical committee

From:Brian Dees

Intel Corporation

2111 NE 25th Ave

MS: JF2-53

Hillsboro, OR97124

Phone: (503) 712-7761

Email:

Date:June 16, 2005

1Introduction

In the case of a PIO command that has anSerial ATA interface CRC error, there is not currently a standard defined response detailing the values in the Error field in the returned status from the device. This document intends to define an expected error response from the device when anSATA interface CRC error occurs on a PIO command, essentially handling the error in the same way as if it were a DMA command.

This proposal accommodates the proposed changes in both ATA/7 and ATA/8 documents. The ATA/7 changes are proposed as an inclusion into the existing ATA/7 errata being drafted (document e05108rX).

2Proposed ATA/7 Command Set Changes

Insert the following material into the Error Outputs material for all PIO data-out commands including DOWNLOAD MICROCODE, SECURITY DISABLE PASSWORD, SECURITY ERASE UNIT, SECURITY SET PASSWORD, SECURITY UNLOCK, SET MAX SET PASSWORD, SET MAX UNLOCK, SMART WRITE LOG, WRITE BUFFER, WRITE LOG EXT, WRITE MULTIPLE, WRITE MULTIPLE EXT, WRITE MULTIPLE FUA EXT, WRITE SECTOR(S), WRITE SECTOR(S) EXT, WRITE STREAM EXT in section 6:

“The device may return error status if an serial Interface CRC error has occurred.

<NOTE – Additional change to be made in the appropriate table for each command to label the ICRC bit (bit 7) instead of listing it as “na”.>

Error Register –

ICRC may be set to one if aserial interface CRC error has occurred.“

Insert the following material into the Error Outputs material for all PIO data-in commands including IDENTIFY DEVICE, IDENTIFY PACKET DEVICE, READ BUFFER, READ LOG EXT, READ MULTIPLE, READ MULTIPLE EXT, READ SECTOR(S), READ SECTOR(S) EXT, READ STREAM EXT, SMART READ DATA in section 6:

“The device may return error status if an serial Interface CRC error has occurred. Note that there is no defined mechanism for a device to return an ICRC error status that may have occurred during the last data block of a PIO-in data transfer, there may be other mechanisms in which a host can verify that an Interface CRC error occurred in these cases.

<NOTE – Additional change to be made in the appropriate table for each command to label the ICRC bit (bit 7) instead of listing it as “na”.>

Error Register –

ICRC may be set to one if aserial interface CRC error has occurred.”

3Proposed ATA/7 Parallel Transport Changes

Insert the following sentence into sections 11.5 and 11.6 in the ATA/7 Command Set:

“Following anSerial ATA interface CRC error on a Data FIS, if the device transmits a Register – Device to Host FISresponse that updates the Status Register it may set the bit 7 (i.e. ICRC bit) to one in the Error Register.”

4Proposed ATA/7 Serial Transport Changes

Insert the following sentence into section 16.5.2.2 (Transmission section which still needs to be added) in the ATA/7 Serial Transport:

“Following a Serial ATA CRC error on a Data FIS, if the device transmits a Register – DevicetoHost FIS that updates the Status Register it shall set the ERR bit to one and both the BSY bit and DRQ bit cleared to zero in the Status Register, and the ABRT bit set to one in the Error Register. It is recommended for the device to also set the bit 7 (i.e. ICRC bit) to one in the Error Register.”

Insert the following sentence into section 16.5.2.3 (Reception section which still needs to be added) in the ATA/7 Serial Transport:

“There is no Register – DevicetoHost FIS transmitted after a Serial ATA CRC error on the last Data FIS of a PIO-in command nor following a Serial ATA CRC error on the ATAPI command packet transfer. Thus, there is no mechanism for the device to indicate a Serial ATA CRC error to the host in either of these cases. The host should check the SError register to determine if a Link layer error has occurred in both of these cases.”

5Proposed ATA8-ACS Changes

Insert the following sentence into sections 5.6 and 5.7 in the ATA/8 Command Set (d1699r1c):

“Following anSerial ATA interface CRC error on a Data FIS, if the device transmits a Device-to-Host FISresponse that updates the Status Register it may set the bit 7 (i.e. ICRC bit) to one in the Error field.”

Make the following change to section 6.3.6:

“6.3.6 Interface CRC (ICRC)

Interface CRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable to Multiword DMA transfers. The content of this bit may be applicable to PIO data transfers forthe both Parallel and Serial transports.”

Insert the following material into the Error Outputs material for all PIO data-out commands including DOWNLOAD MICROCODE, SECURITY DISABLE PASSWORD, SECURITY ERASE UNIT, SECURITY SET PASSWORD, SECURITY UNLOCK, SET MAX SET PASSWORD, SET MAX UNLOCK, SMART WRITE LOG, WRITE BUFFER, WRITE LOG EXT, WRITE MULTIPLE, WRITE MULTIPLE EXT, WRITE MULTIPLE FUA EXT, WRITE SECTOR(S), WRITE SECTOR(S) EXT, WRITE STREAM EXT in section 7:

“The device may return error status if an serial Interface CRC error has occurred. See Table TBD.”

Insert the following material into the Error Outputs material for all PIO data-in commands including IDENTIFY DEVICE, IDENTIFY PACKET DEVICE, READ BUFFER, READ LOG EXT, READ MULTIPLE, READ MULTIPLE EXT, READ SECTOR(S), READ SECTOR(S) EXT, READ STREAM EXT, SMART READ DATA in section 7:

“The device may return error status if an serial Interface CRC error has occurred. See Table TBD. Note that there is no defined mechanism for a device to return an ICRC error status that may have occurred during the last data block of a PIO-in data transfer, there may be other mechanisms in which a host can verify that an Interface CRC error occurred in these cases.”

Insert the following table into section 8.3:

Table TBD – PIO Data Interface CRC Error

Word / Name / Description
00h / Error
Bit / Description
15:8 / Reserved
7 / Interface CRC - See clause 6.3.6.
6 / N/A
5 / N/A
4 / N/A
3 / N/A
2 / Abort – See clause 6.3.1.
1 / N/A
0 / N/A
01h / Count / Reserved
02h-04h / LBA / Reserved
05h / Status
Bit / Description
15:8 / Reserved
7:6 / Transport Dependent - See clause 6.2.11.
5 / N/A
4 / N/A
3 / Transport Dependent - See clause 6.2.11.
2:1 / N/A
0 / Error – See clause 6.2.3.

6Proposed ATA8-AST Changes

Insert the following sentence into section 7.5.3.3 (Transmission section which still needs to be added) in the ATA/8 Serial Transport (d1697r0b):

“Following a Serial ATA CRC error on a Data FIS, if the device transmits a Device-to-Host FIS that updates the Status Register it shall set the ERR bit to one and both the BSY bit and DRQ bit cleared to zero in the Status field, and the ABRT bit set to one in the Error field. It is recommended for the device to also set the bit 7 (i.e. ICRC bit) to one in the Error field.”

Insert the following sentence into section 7.5.3.4 (Reception section which still needs to be added) in the ATA/8 Serial Transport (d1697r0b):

“There is no Device-to-Host FIS transmitted after a Serial ATA CRC error on the last Data FIS of a PIO-in command nor following a Serial ATA CRC error on the ATAPI command packet transfer. Thus, there is no mechanism for the device to indicate a Serial ATA CRC error to the host in either of these cases. The host should check the SError register to determine if a Link layer error has occurred in both of these cases.”

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