A Simple Guide to the Cadence tool
1. Introduction
The objective of this tutorial is to give you an overview to (1) setup the Cadence and Synopsys hspice tools for your account in IST 218 Lab, (2) use the schematic editor, (3)use the hspice tool, (3) use the chip layout editor - Cadence Virtuoso, and (4) use DRC, Extract, LVS tools. This guide may be updated as needed during the semester.
2. Set up the tool environment
Before you can start using design tools, there are a few configuration files needed in your working directory. These files determine the environment in which tools run, and what libraries are to be included in your designs. The setup given below is for UNIX machines in Lab 218. Some UNIX commands will be included in this tutorial. Your are recommended to get familiar with basic UNIX commands to work efficiently.
Step1.
Login to a machine in room 218 IST Building. Bring up a terminal window where you can type a UNIX command. Then type the following:
% /home/faculty/Kyusun/c411/bin/class411setup
This setup needs to be done, only once for this semester.
Now for the setup effect, you logout and login again.
Step 2.
Make your own working directory for CMPEN 411 class. I made:
% mkdir c411
The “c411” is the name of your working directory. You can use any name you like.
Step3.
Change your current directory to c411 by typing:
% cd c411
Then, start the Cadence tool by typing the following:
% virtuoso
Then the CIW (Command Interpreter Window) and the library manager should pop up.
Figure 1 CIW Window
Figure 2 Library manager
If you can find libraries named NCSU_XXXX in the library manager, the Cadence tool and NCSU CDK are successfully set up. Note that, for some machines in Lab-218, the library manager could not be used. You may see the following warning prompt in CIW.
“*WARNING* Unable to start up library manager (libManager.exe) after 60 tries. There may be an access or network problem. Start the library manager from an Unix Shell window to test the accessibility. Variable ddsvMPSTimeOut (60) can be set to increase or decrease the number of attempts.”
It doesn’t mean the setup failed. You can also use the File->Open… to find libraries named NCSU_XXXX.
I have found useful the tutorial posted at:
We use latest Cadence tool, however the almost all the older Cadence schematic and layout editing tool procedures are the same.
3. Generate schematic
In this section, we will create our own library and generate a schematic of inverter.
Step1.
Create a library that holds all our designs named mylib.
In the CIW window,
a) Select File -> New -> Library.
b) Enter the library name mylib.
c) Select the option Attach to an existing technology library.
Figure 3 Create a library
d) Press OK, another window will pop up. Choose the library NCSU_Techlib_aim06 and press OK. Then, a library using the AIM 0.6um technology is created.
Figure 4 Attach a existing library.
Step2.
Create a new schematic view of inverter.
a) Select File -> New -> Cellview.
b) Choose mylib and enter the cell name invin the pop-up window.
Figure 5 Create a new shematic
Schematic editor will pop up.
Figure 6 Start the schematic editor
Create instance of nmos/pmos from the analogLib library.
On the schematic editor, select Create -> Instance or use toolbar.
Choose library NCSU_Analog_Parts in the pop-up Component Browser window.
Choose pmos from the P_Transistors directory.
Figure 7 Components Browser
Then, the Add Instance window will pop up as the following figure. Leave all parameters as default. Then, place the pmos instance. Similarly, place pmos, vss and vdd. Note that the vss and vdd are under the directory of Supply_nets . After placing an instance, press “ESC” to exit the placing mode.
Figure 8 pmos instance
Figure 9 vdd instance
Create -> Pin or use toolbar . Choose appropriate direction.
Figure 10 Add pin
Add wire to the source of nmos/pmos, pin, etc to connect them together. You can select Create -> Wire (narrow) or use toolbar .
Check the design. Select Check -> Current Cellview to check the design. Errors will be displayed in the CIW. Correct any errors.
You can find further instruction from “Help” option in CIW. There are many detailed tutorials in this option.
4. Generate netlist from the schematic and simulate it with HSPICE
Step1.
Open the schematic view of inverter.
Step2.
Select Launch -> ADE L, the Analog Design Environment window pop up.
Figure 11 ADE Window
Step3.
Select Setup->Model libraries, add two models “amio6N” and “ami06P” from ncsu/models/hspice/public/publicModel/
Figure 12 Add models
Step4.
Select Simulation->Netlist->Create to generate the following netlist:
Figure 13 Generated netlist window
Step5.
Save the file as inv.sp, and add the following lines before the “.END”
.option post
Vdd vdd! vss! 1.8
V1 vss! 0 0
Vin in vss! PWL 0NS 1.8 4.00NS 1.8 4.2NS 0.00V 6.00NS 0.00V
+ 6.2NS 1.8 8.00NS 1.8 20.00NS 1.8
Cload out 0 20fF
.trans 20ps 20ns
.measure tpdr
+ TRIG v(in) VAL=0.9 FALL=1
+ TARG v(out) VAL=0.9 RISE=1
.measure tpdf
+ TRIG v(in) VAL=0.9 RISE=1
+ TARG v(out) VAL=0.9 FALL=1
.measure tpd param='(tpdr+tpdf)/2'
Step6.
Save the file and simulate it with the command:
% hspice inv.sp
The tpd value in the result is the propagation delay of the inverter.
5. Generate layout
In this section, we will draw the layout view of the inverter.A layout describes the masks from which your design will be fabricated. The layers in a layout describe the physical characteristics of the device and have more details than a schematic. Therefore, layout verification of your design is critical. There are two types of layout design: Full-Custom and Automated. Full-custom layout is when the user physically draws all of the layers for the individual transistor. This is a very tedious process, but it usually enables results in a compacter design than the automated process. The automated process, on the other hand, is done by instantiating standard cells (reusing basic blocks) and usually takes more area but it is much faster. We only introduce custom layout design here.
You should follow MOSIS SCMOS design rule for AIM 0.6µm:
The inverter consists of three parts -- p-transistor, n-transistor, and connections.
5.1 Generate layout with macro in the library
Step1.
Create a layout view for the inverter.
a) Select File -> New -> Cellview.
b) Choose mylib, select the cell name inv, and select layout view.
Figure 14 Create layout view
c) Click OK. LSW and Layout Editor windows will pop up.
d) Setting Display Parameters:
Select Options -> Display.
Set the following options: (1) Pin names: On (2) Display levels: From: 0 To: 20
Figure 15 Set display
Step2.
Create a instance of pmos transistor.
1. Select Create->instance.
2. Choose NCSU_TechLib_ami06, select the cell name pmos, and select layout view.
3. Place the pmos in the layout editor and get the following layout:
Figure 16 pmos instance
Step3.
Place a nmos as in step2.
Step4.
Draw the Substrate-contact of pmos
1. Select the pselect layer from the LSW window; we will draw the pselect enclosing the substrate (vss = ground) contact for the N transistor
2. Select the Create->Rectangle
3. Draw the pselect on the cellview; it will have to enclose the contact p-active by at least 0.6.The pselect abuts directly to the nselect of the N transistor, but they should not overlap.
4. Select the pactive layer from the LSW window
5. Draw the n-island on the cellview to be 1.2 wide by 1.5 tall; it must be enclosed by the pselect by 0.6.
6. Add contacts in the center of the substrate-contact island.
Step5.
Draw the Substrate-contact of nmos as in the previous step and get the following layout.
Step6.
1. Connect the source of p-transistor to the well-contact using the metal 1 layer.
2. Connect the source of n-transistor to the substrate-contact with the metal 1.
3. Add a contact to the gate (poly)
Figure 17 Layout of inverter
5.2 Generate layout layer by layer
Step1.
Same as step1 in 4.1
Step2.
Layout of P-transistor with L=0.6µm and W=1.5 µm.
Since we are using the Nwell process technology, the substrate will be p-substrate.
We will create a pmos transistor first. To do that we need an Nwell in which the pmos
transistor will be formed.
a) Draw the well
1．Select the n-well layer from the LSW window
2. Select the Create->Rectangle (or use hotkey R).
3. Draw the n-well on the cellview to be 7.2 wide by 7.2 tall.
b) Draw the p- select regions for the p transistor
1. Select the pselect layer from the LSW window; we will draw the pselect enclosing the transistor
2. Select the Create->Rectangle.
3. Draw the pselect on the cellview; 4.8 wide and 2.7 tall; its Left- and
Right-edges should be 0.6 away from well edges. The pselect should be placed within the n-well, even if the size should vary (you can use the Edit->move or hotkey m command to move the layer) .
c) Draw Diffusions
1. Select the pactive layer from the LSW window; draw the active region of the p-device with size 1.5 X 3.6
2. Add a contact in the center of the well-contact island with the size 0.6X0.6
d)Similarly, draw the nmos transistor and connect them.
e) Draw the substrate-contact as in step 4 of 4.1.
f) Draw metal Connections as in step 6 of 4.1 and get the same layout as in figure 14.
5.3DRC rule check.
DRC is used to check that all process-specific design rules (such as spacing) have been met. There are process-specific design rules that describe how close layers can be placed together and what the sizes of the areas can be. These rules are giving the minimum requirement to avoid a catastrophic failure of your circuit due to fabrication faults. You can use the following MOSIS SCMOS design rules as a guideline. The design rules are different for different processes.
In the layout editor, select Verify-> DRC
Figure 18 DRC
If your design has violated any design rules, DRC will reports the errors in the CIW.
Errors are indicated by the markers (white color) on the circuit. You may then proceed to correcting the errors according to the design rules. For huge layouts, the marker might not be easily located. To find markers, choose Verify -> Markers -> Find in layout window.
A pop-up menu will appear. Select on the Zoom to Markers box.
Click on the Apply button and Cadence will zoom in to the errors or warnings as desired.
6. Generate netlist from the layout and simulate it with HSPICE
Step1.
Open the layout view of inverter.
Step2.
Get the extracted view of the layout:
Select Verify -> Extract
Click the Set Switches button.
Select Extract_parasitic_caps option. If you use capacitors or resistors, like in many
analog applications, select Extract_cap and Extract_resistor also.
Step 3
Open the extracted file. Open -> cell name: my_inv -> view name: extracted. You will
see a extracted view:
Figure 19 Extracted View
Step4.
Similar to section 4, Select Launch -> ADE L, and select models
Figure 20 ADE Window
Select Setup->Model libraries, add two models “amio6N” and “ami06P” from ncsu/models/hspice/public/publicModel/
Figure 21 Add models
Step5.
Select Simulation->Netlist->Create to generate the following netlist. Compare with that in section 4.
Figure 22 Generated netlist window
Step5.
Save the file as inv_layout.sp, and add the following lines before the “.END”
.option post
Vdd vdd! vss! 1.8
V1 vss! 0 0
Vin in vss! PWL 0NS 1.8 4.00NS 1.8 4.2NS 0.00V 6.00NS 0.00V
+ 6.2NS 1.8 8.00NS 1.8 20.00NS 1.8
Cload out 0 20fF
.trans 20ps 20ns
.measure tpdr
+ TRIG v(in) VAL=0.9 FALL=1
+ TARG v(out) VAL=0.9 RISE=1
.measure tpdf
+ TRIG v(in) VAL=0.9 RISE=1
+ TARG v(out) VAL=0.9 FALL=1
.measure tpd param='(tpdr+tpdf)/2'
Step6.
Save the file and simulate it with the command:
% hspice inv_layout.sp
The tpd value in the result is the propagation delay of the inverter. Compare with the result from section 4.
More update is on the way for the hspice.