Hardware Implementation of a NRZL and NRZI Encoder

Experiment No. (2)

Hardware Implementation of a NRZL and NRZI Encoder

Objective

The aim of this experiment is to design and implement a NRZL and NRZI Encoder in Spartan 2 E FPGA.

Procedures

1. Start a new VHDL project and choose “Spartan 2E” as the device family, “XC2S200e” as the device, “PQ208” as the package, and “-6” as the speed.

2. Write the VHDL code for a NRZL and NRZI Encoder in one design as shown in fig.

3. Synthesis your VHDL and make sure that there is no syntax error.

4. Simulate your design for different data inputs with input clock, and check the NRZL_out and NRZI_out.

5. Check the RTL Schematic for your design.

Laboratory Assignment

Design and simulate the NRZL and NRZI Decoder.