Chip Design News
EVE Adds New Applications for Leading SoC Emulation Platform Environment
Evolves Emulation into Comprehensive Hardware/Software Co-Verification Solution
SAN JOSE, CALIF. –– EVE today announced a variety of new software to expand the capabilities of its ZeBu system-on-chip (SoC) emulation platform, including power-aware verification, post-run debugging, two vertical application validation platforms, low-power and Flash memory models, and electronic system level (ESL) tool interfaces.
“Today’s emulation platforms have evolved into complex verification environments to address hardware/software integration and embedded software validation of large designs,” remarks Luc Burgun, EVE’s chief executive officer and president. “ZeBu has evolved as well and is now the industry trendsetter, as well as market leader, meeting EVE’s goal to offer the most comprehensive and commercially available hardware/software co-verification solution.”
A new power-aware verification package for ZeBu enables functional verification of power switching in low-power designs. Power islands can be turned on/off dynamically to ensure that power switching does not adversely affect a design’s functional integrity. The first release shipping now supports the Unified Power Format (UPF) standard.
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Nufront’s Third-Generation Mobile Applications Processor Powered by Cadence DDR3/3L/LPDDR2 Memory Interface IP Solution
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Nufront’s NS115 chipset integrated the Cadence configurable DDR3/3L/LPDDR2 Memory Controller and Hard PHY IP core in its dual-core ARM® Cortex™-A9 based mobile applications processor. The TSMC 40nm LP 32-bit DDR3/3L/LPDDR2 interface features a data rate of up to 800Mbps while providing the automated traffic-based power management and efficiency critical to the ultrabook, tablet and smartphone markets. Fully compliant with the latest published specifications from JEDEC, the Cadence IP core for DDR3/3L/LPDDR2 memory enabled Nufront to reduce design risk and speed development of their chipset.
“Our third-generation dual core mobile computing chip, the NS115 delivers the performance, power efficiency and quality required by the tablet and smartphone market. It was selected for use in tablets from several local OEMs that were recently demonstrated at the Hong Kong Electronics Fair,” said Rock Yang, vice president of marketing, Nufront. “Cadence has developed an innovative, high-quality DDR3/3L/LPDDR2 IP core architecture that gives us the configuration flexibility necessary to meet the specific needs of our customers.”
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Professional Circuit Designs, Ltd. Standardizes on Mentor Graphics PCB Design-Through-Manufacturing Technologies for Design and Consulting Services
WILSONVILLE, Oregon – Mentor Graphics Corporation, (NASDAQ: MENT), the worldwide market and technology leader in printed circuit board (PCB) design-through-manufacturing software, today announced that Professional Circuit Designs (PCD), Ltd., based in Winchester, U.K. has standardized on the Mentor Graphics® PCB design-through-manufacturing product flow, including the Valor® NPI tool. PCD specializes in PCB place & route, schematic entry, pre- and post-layout of PCB signal integrity simulation, library development and now new product introduction (NPI) design checking for PCB manufacturing and assembly.
Established in 1997, PCD, Ltd. is the largest PCB design and consulting firm in the U.K. serving customers throughout Europe, the United States and Australia. They exclusively use the Mentor Graphics PADS®, Board Station® XE, Expedition® Enterprise, HyperLynx® SI, and Valor NPI products. Now, with the integration of the Valor NPI tool, PCD customers will be able to capture all PCB design-for-manufacturing, fabrication, assembly and test data into a unified data structure with the Valor ODB++ data exchange format. As the de facto standard for unified data exchange between PCB design and manufacturing, ODB++ establishes a continuous, automated and traceable engineering process that reduces time and eliminates costly errors.
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AMD Selects Synopsys as a Verification IP Partner
Expands Collaboration to Further Accelerate SoC Verification
MOUNTAIN VIEW – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced a multi-year agreement to provide Advanced Micro Devices, Inc. (AMD) with its next-generation Discovery™ Verification IP (VIP). Based on the new VIPER architecture, the recently announced Discovery VIP family provides inherent performance, ease-of-use and extensibility to speed and simplify verification of the most complex system-on-chip (SoC) designs. This agreement covers a variety of VIP titles including USB 3.0, ARM® AMBA® AXI™ interconnect, SATA 3.0, PCI Express® Gen 3, and MIPI, as well as Synopsys’ Protocol Analyzer, a unique protocol-aware SoC debug environment.
"In our verification environment for Southbridge SoCs and IP cores, we utilize several interfaces, including AXI3™ and USB 3.0. After an extensive evaluation, we selected Synopsys’ next-generation Discovery VIP for several of our leading SoC designs," said Thomas Bodmer, manager of design engineering at AMD. "With Discovery VIP, we have seen benefits in minimizing our simulation runs and achieving higher coverage. We have used Synopsys’ Protocol Analyzer technology to narrow down protocol violations and debug the root causes."
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Etron Selects Berkeley Design Automation Analog FastSPICE™ Platform
SANTA CLARA, CA, — Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that Etron Technology, Inc., a world-class fabless IC design and product company specializing in specialty memory and system chips, has selected the company’s Analog FastSPICE™ (AFS) Platform for characterization and verification of their memory designs for low-power and consumer applications.
“Etron memory applications require circuit verification with the highest possible accuracy to ensure high quality die,” said Bor-Doou Rong, Vice President at Etron. “We selected the Analog FastSPICE Platform because it delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and helps us meet the quality and yield goals for our Known-Good-Die (KGD) and packaged buffer memory designs.”
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Mindspeed and China Mobile Collaborate for TD-SCDMA/TD-LTE Small Cell Solutions
Mindspeed’s System-on-Chip (SoC) Processors to Power China Mobile’s Small Cell Base Stations
NEWPORT BEACH, Calif. – Mindspeed Technologies, Inc. (NASDAQ:MSPD), the industry leader in technology for small cell base stations, today announced that it will form a joint development lab with China Mobile Communications Corporation to support the operator’s recent deployment of Time Division Synchronous Code Division Multiple Access (TD-SCDMA) femtocells.
“With the close support and collaboration from chip vendors and infrastructure companies like Mindspeed, femtocell technologies in China Mobile’s TD-SCDMA network have achieved commercial deployment. This joint development brings a significantly improved customer experience and further demonstrates that small cells will play important roles in wireless broadband services,” said Gu Yihong, assistant general manager at China Mobile Jiangsu Suzhou Branch. “The convergence of TD-SCDMA, TDD-LTE, GSM and Wi-Fi is a fast evolving technology trend, and we appreciate TD-Femto ecosystem companies like Mindspeed that are driving this shift with mature solutions.”
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Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications
Complete IP Subsystem Enables Fast Development of SoCs at Lower Cost
SAN JOSE, CA – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today launched the industry’s first IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive (SSD) market. The solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem. The subsystem is the industry’s first to feature fully-integrated component IP, including the NVM Express Controller, firmware, and the corresponding NVMe and PCIe models from the Cadence Verification IP Catalog. This high level of integration enables easy implementation of NVM Express in SoC designs.
NVM Express is a specification that will speed the broader adoption of PCI Express-based SSDs by improving performance and reducing power consumption and latency compared to existing SATA/SAS interfaces or proprietary PCI Express implementations. The NVM Express specification defines the register interface, command set, and feature set to provide a scalable interface for PCI Express-based SSDs.
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Tanner EDA and Aldec Deliver High-Performance A/MS Solution for Mixed-Signal IC Design and Verification
Seamless interface allows both analog and digital engineers to solve complex analog/mixed-signal verification problems
Design Automation Conference 2012
MONROVIA, Calif.– Tanner EDA, the catalyst for innovation in the design, layout and verification of analog and mixed-signal integrated circuits (ICs), and Aldec, Inc., an industry leader in mixed VHDL, Verilog and SystemVerilog simulation, have collaborated to deliver an integrated co-simulation solution for analog and mixed-signal (A/MS) design. Tanner EDA’s new HiPer Simulation A/MS offers their T-Spice analog design capture and simulation tool together with Aldec’s Riviera-PRO™ mixed language digital simulator. The solution allows both analog and digital designers to seamlessly resolve A/MS verification problems from one cohesive, integrated platform.
Creating and verifying A/MS integrated circuits is a challenge. Spice-based simulation provides the accuracy needed for the analog design, but is too slow to handle the digital part. Event-driven digital simulation provides the necessary speed to simulate the digital portions, but fails when dealing with the analog parts. As A/MS designs grow in complexity and business pressures force design teams to shorten time to market and reduce re-spins, a new solution for mixed analog and digital co-simulation, with a robust feature set and an affordable price, is needed.
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Samsung Now Producing Highest Density Mobile LPDDR2 Memory Using 20nm-class Technology – an Industry First
SEOUL, South Korea - Samsung Electronics Co., Ltd., a global leader in advanced semiconductor technology solutions, announced today that it has begun producing the industry’s first four gigabit (Gb), low power double-data-rate 2 (LPDDR2) memory using 20 nanometer (nm) class* technology. The mobile DRAM (dynamic random access memory) chip, which went into mass production last month, will help the market to deliver advanced devices that are faster, lighter and provide longer battery life than today’s mobile devices.
“Samsung began expanding the market for 4Gb DRAM last year with the first mass-produced 30nm-class DRAM, and now we are working on capturing most of the advanced memory market with our new 20nm-class 4Gb DRAM,” said Wanhoon Hong, executive vice president, memory sales & marketing, Samsung Electronics. “In the second half of this year, we expect to strongly increase the portion of 20nm-class DRAM within our overall DRAM output to make the 4Gb DRAM line-up the mainstream product in DRAM production, and therefore keeping the leadership position in the premium market and strengthening our competitive edge.”
As large-screen tablets and smartphones equipped with quad-core CPUs lead rapid growth of the mobile market, there is greater demand for more energy-efficient and higher-capacity memory products that guarantee longer battery life, as well as faster processing speed.
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EVE’s ZEMI-3 Methodology Used by Fujitsu Microelectronics Solutions to Implement Integrated Algorithm-to-Emulation Flow
Reports 1,300X Acceleration on Wireless Application Design Using High-Level Synthesis
SAN JOSE, CALIF. – EVE, the leader in hardware/software co-verification, today announced that its ZeBu hardware-assisted verification platform and ZEMI-3 transaction-level modeling methodology have been adopted by Fujitsu Microelectronics Solutions Limited of Kanagawa, Japan.
Fujitsu Microelectronics Solutions implemented an integrated algorithmic C verification to register transfer level (RTL) emulation flow for its high-level synthesis (HLS) design methodology.
“An HLS design methodology accelerates functional verification by raising the abstraction level, decreasing the time and cost of RTL design,” remarks Takashi Nishikawa, of the Design Technology Department, Technology Development Division at Fujitsu Microelectronics Solutions Limited. “Accordingly, we are continually improving our HLS design methodology with great success. We built an RTL verification environment using the SystemVerilog DPI-C (Direct Programming Interface-C), and implemented the integrated flow from algorithmic C verification to RTL emulation with ZEMI-3 and ZeBu, deployed since 2006. When we deployed the flow with ZEMI-3 and ZeBu in designing a wireless application, it provided 1,300X acceleration against simulation.”
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Kilopass NVM IP Cores First to Deliver Footprint and Pin Compatibility Across Eight Top-Tier Silicon Foundries for the 130/110nm Process Node
Common Implementation Assures Foundry Mobility at 130/110nm
Process Node for Entire Kilopass XPMTM and GustoTM NVM IP Product
SANTA CLARA, Calif. – Kilopass Technology Inc., a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP), today announced that SoC designers can select any hard IP core—IP supplied as GDSII hard macro—from the entire library of Kilopass XPM (eXtra Permanent Memory) and Gusto NVM IP, drop it into a design for fabrication at any of eight top-tier foundries at the 130/110nm node. Kilopass’ NVM IP common implementation for the eight top-tier silicon foundries at the 130/110nm process node means designers can use the same interface and achieve the same area at all of the eight foundries at the 130/110nm, thus making foundry mobility far simpler than before.
"In the past, it might have been possible to move a design from one foundry to another but the size and interface of the NVM IP block would vary from one foundry’s process to another. Designers would need to tweak the interface, and accept or redesign for differences in area that individual foundry 130/110nm processes produced,” said Lee Cleveland, vice president of engineering at Kilopass Technology Inc. “Kilopass has developed a common implementation at the 130/110nm node that allows all our XPM and Gusto NVM IP cores to be fabricated at any of eight top-tier silicon foundries and deliver the same area using the same interface at each."