ECE 471 - needs faculty review & possibly Cat II.doc Last printed 5/3/2007 1:31:00 PM
ECE 471 – Advanced Digital Logic and Integrated Circuit Design
Catalog Description:
Finite state machine design and analysis, digital system testing and design for testability, high-level hardware description languages, digital integrated circuit design, CMOS scaling and process variability, synthesis vs. custom digital circuit design.
Final project 2007-2008 -- the design of either: Low-Power Register File, with 64 Words x 64bits; 5x5 port, 256-bit Crossbar. Full schematic/custom-layout; simulation. Possible submission of final layout for chip fabrication.
ENFORCED PREREQS: ECE 375, ECE 271.
RECOMMENDED: ECE 472
Credits: 4 Terms Offered: Winter annually
Structure: Two 110-minute lectures per week. Laboratory work - projects on the use of HDL, CAD, and digital circuit design.
Prerequisites:
By course: Enforced Prereqs: ECE 375, ECE 271, Recommended: ECE 472.
By topic: Basic knowledge of combinational digital logic: gates, Boolean algebra, Basic knowledge of sequential digital logic: flip-flops, state diagrams, finite state machine concepts, knowledge of basic combinational and sequential modules: multiplexer, binary decoder/decoder, adder, and binary counter. Emphasis on digital integrated circuit design including power consumption, timing constraints, process variation, synthesis and layout considerations.
Courses that require this as a prerequisite: none
Instructors: Primary: P. Chiang Secondary: Z. Wang
Course Content
· Review of topics in combinational digital logic: boolean algebra, analysis and design.
· Advanced topics in combinational system design: use of CAD, timing characteristics, system decomposition, arithmetic modules, ALU design, use of standard combinational modules.
· Introduction to a Hardware Description Language, focusing on its application to combinational system description, simulation, and synthesis into gate implementations and layout.
· Advanced topics in sequential system design: using sequential modules, timing characteristics, effect of state code on size/speed of the system, modularization, design of complex sequential systems.
· Introduction to digital integrated circuits—gate sizing, power dissipation, rise/fall delay, logical effort and fanout definitions.
· Clock skew, timing jitter, dynamic logic and noise margins, pass-gate logic.
· Design for testability (DFT): definition of DFT, test schemes and types of faults, reducing the cost of testing, scan paths, and built-in self test (BIST).
Measurable Student Learning Outcomes:
Students must demostrate the ability to:
1. Design and analyze median complexity combinational and sequential systems.
(ABET Outcomes: a, c, k)
2. Describe and simulate digital systems using Computer Aided Design Tools (i.e. Hardware Description Language).
(ABET Outcomes: b, c, j, k)
3. Compare the advantages/disadvantages between HDL synthesis and layout versus custom digital circuit design.
(ABET Outcomes: b, e, k, o)
4. Analyze and understand various engineering tradeoffs – process scaling, supply voltage reduction, power consumption, power supply noise, etc.
(ABET Outcomes: b, c, d, j, p)
Evaluation of Student Performance:
Learning Resources:
· Digital Integrated Circuits, 2nd Edition, Rabaey, Chandrakasan, and Nikolic.
Students with Disabilities:
Accommodations are collaborative efforts between students, faculty and Services for Students with Disabilities (SSD). Students with accommodations approved through SSD are responsible for contacting the faculty member in charge of the course prior to or during the first week of the term to discuss accommodations. Students who believe they are eligible for accommodations but who have not yet obtained approval through SSD should contact SSD immediately at 737-4098.
Link to Statement of Expectations for Student Conduct, i.e., cheating policies
http://oregonstate.edu/admin/stucon/achon.htm
Sample Project from Winter 2006-2007.
ECE 471 Final Project
OUT: 2/16/2007
IN: 3/20/2007 (Tentatively)
· Project Part 1: DSP Multiplier-Accumulator Design
· Objective: Design a pipelined, 8 * 4 + 12 bit DSP multiplier-accumulator in a
250nm (or better) CMOS process for a “target” clock frequency of at least 5GHz and
minimum power consumption.
· Target Architecture:
Figure 1: Implementation of Digital Feed Forward Equalizer
Figure 2: Digital Implementation of 8 x 8 multiplier and 16-bit adder of MAC
· Basic Functionality:
The MAC takes an 8-bit input called <A> and another 8-bit input called <B> and multiplies them together to get a 16-bit output called <BM>. The MAC takes a delayed version of <A> called <ADELAY> and adds it to <BM>.
You likely need to add clock latching at every stage of the 8x8 multiplier and the 16-bit Adder. At 10GHz, the cycle time is 100ps, so there is not a lot of time to do computation within this time period.
· What you need to turn in:
o Final, comprehensive project report with all design details. Please state all assumptions made clearly. One report per team member: individual report
o Last day, March 20, Midterm presentation: 20-minute presentation.
o Each team builds one MAC: please share the load equally (team dynamics)
· Target Specifications:
o 20% - %80 edge rate for A,B, CLK = 80p
o Clock frequency => Attempt 100MHz
o Vcc = 2.5V, 0.25um CMOS (unlikely that it is fast enough)
· Minimize power consumption: Figure of Merit is:
Clock Frequency (Gigahertz) / Power (Watts)
· Process Parameters:
o Process: try 0.25um CMOS (although may not be able to get you fast enough)
o
· Design Choices:
o Multiplier: 1) array architecture or Wallace-tree architecture
2) any static of dynamic/domino circuit technique
o Adder: 1) Ripple-Carry, Manchester-tree, Carry lookahead, or
conditional-sum
2) any static or dynamic/domino circuit technique
· Flip-flop: use a conventional flop, or just simple dynamic NMOS pass-gate with inverter (for speed reasons)
· You may need to use a different technology to get this to work at 10GHz. You already have used 0.13um and also 32nm CMOS.
· Start with schematic design of 8x8 multiplier—we will worry about physical layout later.
· Good reference: (ieeexplore.ieee.org): Fang Lu and Henry Samueli. “A 200-Mhz CMOS Pipelined Multiplier-Accumulator Using a Quasi-Domino Dynamic Full-Adder Cell Design”, Journal of solid-State Circuits, vol. 28, No. 2, Feb. 1993
o There are definitely other 8x8 multiplier structures available