Activity 5.3A – Introduction to PLDs

ANSWERS

Purpose

1.To familiarize students with the vocabulary and background on Programmable Logic Devices (PLDs)

Equipment

None

Procedure

Read the following information and highlight the important sections. Then answer the questions in the conclusion section.

Programmable logic devices (PLDs) are used in many applications to replace small-scale integration and medium-scale integration circuits. They reduce the actual number of chips needed, the final cost buying the individual parts and the eventual cost of fabricating the circuit board. All PLDs consist of programmable arrays: a grid of conductors that form rows and columns. There is a fusible link at each connect point. These arrays can be re-programmable or, once programmed, permanently fused – based on the architecture of the chip.

There are 4 basic types of PLDs:

  • PROM – Programmable Read-Only Memory

This PLD consists of a non-programmable AND gate array and a programmable OR array. This device is used primarily as an addressable memory and not as a logic device because of the limitations imposed by the fixed AND gates.

  • PLA – Programmable Logic Array

This PLD has both a programmable logic AND array and a programmable logic OR array. The PLA was developed to overcome some of the limitations of the PROM. As a trade-off, the PLAs have longer delays due to the 2 sets of fusible links from using 2 programmable arrays and more complex circuitry.

  • PAL – Programmable Array Logic

Pals were developed to try and speed up the PLA chips. This PLD has a programmable AND array and a fixed OR array with output logic. The PAL is the most common 1-time programmable logic device and it too uses links which become permanently fused.

  • GAL – Generic Array Logic

The GAL is much like the PAL – it has a programmable AND array and a fixed OR array. The primary difference is that the GAL can be reprogrammed due to the fact that it uses E2CMOS (Electrically Erasable CMOS) instead of permanently fusing links.

Because the GAL is so versatile and can be reused over and over again it is a chip that is commonly found and used. This structure allows any sum-of-products (SOP) logic expression with a defined number of variables to be implemented. This chip is basically a grid of connectors forming rows and columns with an electrically erasable CMOS cell at each cross point rather than a fuse as in a PAL. A cell that is “on” connects the intersection point of its row and column; one that is “off” disconnects the row and the column.

The standard part numbering system for a GAL chip is as follows:

The part always begins with “GAL”, followed by a 2-digit number which indicates the number of inputs, the letter V (to designate a variable-input configuration), and lastly a 1 or 2 digit number that is the number of outputs. Therefore the chip GAL22v10 is: Generic Array Logic, 22 inputs, Variable output configuration and 10 outputs.

There are three components needed to program a PLD. They are:

  • A personal computer
  • a programming software (a compiler)
  • and, a software driven programmer

There are various types of logic compilers, all of which perform a similar function: they process and synthesize the logic design, convert the entered data into an intermediate file and then generate a final output file called a JEDEC file (also called a fuse or cell map).

Some examples of PLD languages are:

  • CUPL (Universal Compiler for Programmable Logic),
  • ABEL (Advanced Boolean Expression Language)
  • Palasm (whose letters don’t form any type of abbreviation)

The programmer used has a zip socket (zero-insertion-force), and uses the JEDEC file created by the compiler. (JEDEC stands for Joint Electronic Device Engineering Council, the group who creates the standard that all compilers and logic programmers use.)

Conclusion

1.What is the difference between a PAL and a PLA?

This PLD has both a programmable logic AND array and a programmable logic OR array while a PAL has a programmable AND array and a fixed OR array with output logic. The PALs are faster than the PLAs.

2.What does GAL stand for?

Generic Array Logic

3.How many inputs and how many outputs does a GAL16v8 have?

16 possible inputs, and 8 possible outputs

4.What is required to program a PLD?

A computer, a compiler language and a chip programmer

5.What is a JEDEC file?

JEDEC stands for Joint Electronic Device Engineering Council. This is a type of file that the programmer understands. It is created by the compiler program.