Active-HDL Simulator Tutorial

  1. Start Active-HDL by double-clicking the icon on the desktop. Check Create new design and click OK. Check Create an empty design and click Next. Select Synopsys FPGAExpress for the Synthesis tool. Select Xilinx Foundation for the Implementation tool. Select XC4000E for the Default Family. Select VHDL for the Default HDL language. Type Lab1a for the Design name. Click Browse and select the CSE670 directory and edit this directory name to be c:\cse670\<your_last_name>\. Click Next and Finish.

  1. Double-click on Add New File in the Design Browser and select the VHDL Source Code Wizard. Click OK. Check Add the generated file to the design and click Next. Type in mux2 for the file name and click Next.
  1. Add the three inputs a[3:0], b[3:0], and sel. Click the up-arrow under Bus to select the bus width for a and b. Add the output y[3:0] and then click Finish.

  1. Copy the VHDL statements from the Lab 1 handout and paste them in the architecture where it says -- <enter your statements here>. Save the program. Compile the program by right-clicking on mux2.vhd and select Compile.

  1. Click on the Structure tab (the center tab at the bottom-left of the window) and then select mux2 as the Top-Level selection.
  1. Click on the New Waveform icon.
  1. Click on Root and drag it to the waveform window. All of the signals in mux2 will be displayed in the waveform window. You can move only selected signals by dragging them from the signal list at the lower-left of the screen.
  1. From the Active-HDL menu select Simulation -> Initialize Simulation.
  1. In the waveform window, right-click signal a and select Stimulators.
  1. In the Stimulators window, select Value as the Type, and type in 16#5 as the Force value. Click Apply. This will set the 4 bits of a to the hex (base 16) value of 5. Click Close.
  1. Move the Stimulators window so that you can click on signal b in the waveform window and set its value to a hex A (16#A). Click Apply. Click on signal sel in the waveform window and select Clock as the Type, and change the Frequency to 50MHz. Click Apply. Click Close.
  1. Click on the Run For icon to run the simulator for 100 ns.
  1. You can display the 4 bits of signal y by clicking on the + sign to the left of the signal name.
  1. To save the waveform, select File -> Save As and type in mux2 for the filename and click Save. This will create the waveform file, mux2.awf. Closing the window will exit Active-HDL.

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