Wireless ECG Monitoriong System

FPGA BASED MONITORING SYSTEM

FPGA Based Monitoring System for Heart Rate and Arterial Oxygen Saturation

Vandana V. Kale, Atika Jain and A.D.Rahulkar

Department of Instrumentation and Control, All India Shri Shivaji Memorial Society’s Institute of Information Technology,

University of Pune, Pune 411 001, Maharashtra

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Abstract -- Heart Rate and Arterial Oxygen Saturation (SpO2) measurements play a vital role in operating theatre, intensive care unit, recovery room and general wards. The conventional monitoring systems for these parameters use discrete ICs and analog notch filter to remove 50Hz noise signal. These systems are complex with larger printed-circuit-board area.

In this paper, a new approach is proposed in order to measure SpO2. TheUniversal Asynchronous Receiver Transmitter is designed and implemented using VHDL and Xilinx FPGA respectively.

The benefit of the proposed work is to convert serial SpO2 data into parallel data so as to process further data effectively.

Also, we have designed Notch Filter in VHDL in order to remove 50 Hz noise signal from Electrocardiogramsignal.

This approach is intended to overcome the limitations of conventional monitoring system.

Keywords:- FPGA, UART, FIR, Xilinx and ECG signal.

Introduction

MANY developments in the medical system technology gave birth to monitoring systems based on Programmable Logic Devices (PLDs) (e.g.Field-programmable gate arrays and Complex Programmable Logic Devices ).

It is well known thatFPGAs are widely used in the implementation of fast digital systems for retrieval, processing, storage, and transmission of data.Xilinx, Altera, Lattice, Actel, Quick logic are some of the companies making FPGAs in the world[1-2].

Electrocardiogram (ECG) is a graphical record of the electrical signals generated by the heart. It is used clinically to diagnose various diseases and conditions associated with the heart.

Oxygen is carried in the bloodstream mainly bound to hemoglobin. One molecule of hemoglobin can carry up to four molecules of oxygen(which is 100% saturated with oxygen). The average percentage saturation of a population of hemoglobin molecules in a blood sample is the oxygen saturation of the blood.

Verilog and Very High Speed Integrated Circuit HDL (VHDL) are hardware description languages to design digital logicusing FPGAs and CPLDs. FPGAs provide optimal device utilization through conservation of board spaceand system power [3-4].

The existing system uses discrete ICs like decoder, latches, tri-state-buffers, four UARTs, three microcontrollers, analog to digital converter, level converter etc for monitoring ECG, NIBP and SpO2 signal. So it is required to have modification in the system so as to make it compact, flexible and faster responding.

In this work, we developed UART based on FPGA to reduce the complexity of the conventional medical system.

II.Proposed System

The aim of this work is to designand implement some part of the MPARA system in VHDL and Xilinx FPGArespectively.

In this paper, UART is designed and implemented using XC2S50 Spartan II FPGA. Also digital filter is designed in VHDL so as to remove 50Hz noise from ECG signal. Thegeneralized block diagram of the proposed MPARA system is shown in Fig.1.

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Figure 1.Generalized BlockDiagram of theMonitoringSystem.

A. Hardware Design

Specifications of proposedmonitoring system are:

1)The system is flexible.

2)UART has three sections:Variable Baud Rate Generator, Transmitter and Receiver section.

The following Registersareimplemented in UART

Receiver Buffer Register (Read Only).
Transmitter Holding Register (Write Only).
Interrupt Enable Register (Write Only).
Interrupt Identification Register (Read Only).
Line Control (Write /Read).
Line Status Registers (Read Only).
Modem Control and Modem Status Registers (Write /Read).
Divisor Latch LSB (Write Only).
Divisor Latch MSB (Write Only).

3) URAT Implements all standard serial interface protocols.

5, 6, 7 or 8 bits per character.
Odd, Even or no parity detection and generation.
1 or 2 stop bit detection and generation.
Variable baud rate generator: 300 bps to 921.6kbps.
False start bit detection.

4) FIR filter design specifications

The FIR filter removes 50 Hz noise signal from ECG signal. Using following specifications impulse response coefficients are calculated.

Sampling Frequency: 147 Hz.
Stop band Attenuation: 65dB.
Pass band Ripple: 0.5 dB.

LowerPass band Frequency: 47 Hz.
UpperPass band Frequency: 53 Hz.
Lower Stop band Frequency: 49.5 Hz.
Upper Stop band Frequency: 50.5 Hz.

UART Design: The FPGA’s UART pin diagram is shown in Fig 2. UART uses 20 pins out of 140 user available I/O pins of XC2S50 FPGA.The two clock pins clk and clk_proc are global clock pins. D0-D7 are bidirectional data pins and other I/O pins can be used as input, output or input.

TABLE 1 -- I/Os USED IN FPGA’S UART

I/O Name / I/O / Function
Proc_clk / I / Master clock (11.0592MHz)
Clk / I / Uart clock(1.8432MHz)
D(7 downto 0) / I/O / Bidirectional 8- bit Data Bus
A(2 downto 0) / I / 3-bit address bus
We / I / Write enable-active low
Cs_asy / I / Chip select-active low
Re / I / Read enable-active low
Reset / I / Asyncronous reset –active high
Intr / O / Interrupt signal
Txd / O / Serial transmission line
Rxd / I / Serial receiving line

Figure 2. Pin diagram of UART using XC2S50 Spartan2 FPGA.

FPGA BASED MONITORING SYSTEM

Filter Design

It requires 21 I/O pins of XC2S50 FPGA.The clock pin clock is global clock pin. The data pins Din0-Din7 are input data pins and Dout0-Dout7 are output data pins. RD is the active low input signal of FIR Filter.

Microcontroller 89C52 sets this signal to logic zero to read the Dout0-Dout7 (filtered) output data. ADC_EOC is the input signal of FIR filter. The high one of this signal indicates that the digitized data byte (output of ADC) is available and FIR filter can read it. ADC sets this signal to logic one state.

FIR_done is the Output Signal of FIR filter,logic one of this signal indicates that filtered data is available and 89C52 canread it. Then 89C52 generates RD signal to read the filtered data.

Figure 3. Pin diagram of Filter using XC2S50 Spartan2 FPGA.

B. Software Design

The flow chart of real time FIR filter designed to remove 50 Hz noise from ECG signal is shown inFig.4.

III.Implementation of Proposed System

Integrated Software Environment (ISE) is Xilinx design software.It enables to start design of UART and FIR filter

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with different source types. ModelSim is a simulation and

debugging tool for verifying the functionality of these designs. MATLAB 7.0.1 is used to find filter coefficients using Filter Design and Analysis Tool (FDATool).

Figure 4. Flow chart of real time FIR filter.

Implementation of UART

The three sections of UART are synchronous with MPARA system’s clock. The variable baud rate is generated using clock frequency of 1.8432 MHz.

Transmitter Section

The functionality of Transmitter section is as follow:

The transmitter section waits for load signal to load the input data in transmitter holding register.
Initially Transmitter shift start signal which is logic zero bit. Then Transmitter shifts every bit of input data. Transmitter section calculates the parity i.e. even parity, odd parity or no parity. This shifting process occurs for every bit when transmitter section is enabled. The enable signal of transmitter is baud rate generator’s logic one (output) signal. At last, it shift stop bit (either one or two) which is logic one bit.

The simulating waveform of Transmitter Section of UART is shown in Fig 5.

Receiver Section

The functionality of Receiver section is as follow:

Receiver section waits for the falling edge of RXD signal (start bit)
It sample RXD at mid bit & verify start bit
Then it receives all data bits along with parity bit:
It sample & test stop bit
Then it generates interrupt signal. When microcontroller reads the active high Interrupt signal, it takes data available on 8-bit data lines. Then interrupt signal goes in logically low state.
Receiver section return to idle state (waiting for new start condition).

The simulating waveform of Receiver Section of UART is shown in Fig.6.

Baud Rate Generator section

Variable baud rate from 300 bits per second (bps) to 921.6 Kbps (kilo bits per second) can generate using Variable Baud Rate Generator. The flow of Variable Baud Rate Generator section is as follow

Once the supply is turned on, it starts generating the baud rate with its default value.

The baud rate can be changed by giving desired value in baud rate selection registers (DLL and DLM) externally (using microcontroller).
The baud rate generator can generate baud rates from 300 bps to 921.6Kbps by using reference clock as 1.8432MHz.

Waveform of Baud Rate Generator Section of UART obtained using Modelsim Simulator is shown in Fig.7

IV.Experementation and Results

A. Experimentation

1. Implementation of UART

1. While performing experiments on UART, the functionality of each block of UART is checked.

In case of Transmitter section, 8-bit parallel data has given to Transmitter and checked waveforms on Digital Storage Oscilloscope (DSO). Also the waveforms for data characters with different parity (even, odd or no parity), stop bits (1 or 2. and number of bits in the character (5, 6, 7 or 8 bits) have checked on DSO.Once power supply turns on, Baud rate generator starts to generate baud rate with its default value. By changing the data in baud rate selection register, its baud rate can change. Waveforms of different baud rate (4800bps, 9600bps, 115.2Kbps etc) have seen on DSO. In this case, 1.8432 MHz clock used as reference clock.

2) To check Transmitter and Receiver section of UART, data has taken serially from one host, stored it in register as byte

(i.e. in parallel from) then again converted it into serial form and transmitted to another host, with variable baud rate.

FPGA BASED MONITORING SYSTEM

3. Also, data (1 start bit + 8 data bits + 1 odd parity bit + 1 stop bit) has taken serially from SpO2 module in UART.

Figure5. Waveform of Transmitter Section of UART.

Figure6. Waveform of Receiver Section of UART.

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Figure 7. Waveform of Baud Rate Generator Section of UART.

The Receiver section converted this serial data in parallel data. The transmitter section then converted parallel data in serial form and transmitted data to host with baud rate of 4800bps.

A.2 Filter Design

FDATool of MATLAB calculates the filter coefficients.Its response is shown in Fig. 8.

Figure 8. The Magnitude Response and Phase Response of FIR filter.

FPGA BASED MONITORING SYSTEM

Results

1.UART

XC2S50 Spartan II FPGA device utilization summary is given below

Selected Device: 2s50pq208-5

Number of Slices: : 222 out of 768 28%

Number of Slice Flip Flops: : 177 out of 1536 11%

Number of 4 input LUTs: : 396 out of 1536 25%

Number of bonded IOBs: : 57 out of 144 39%

Number of GCLKs: : 3 out of 4 75%

Total memory usage of the XC2S50 Spartan II FPGA device for UART is 63512 kilobytes.

Waveforms supporting to experimentation of UART are given below.

Data Format = 1 Start bit + 8 data bits + no parity bit

+ 1 Stop bit

8 bit data (101111001) transmitted with 9600bps baud rate and no parity

Data Format = 1 Start bit + 8 data bits + odd parity

bit + 1 Stop bit

8 bit data (01110001) transmitted with 4800bps baud rate and odd parity

2.Filter

Simulating waveform supporting to experimentation of FIR with input array containing 4 inputs and coefficient array of 4 coefficients is given below.

Input data width: 4 bit

Output data width: 16 bit

Coefficient width: 4 bit

Multiplier width: 8 bit

Adder width: 16 bit.

V. Conclusion

This work is one step ahead towards the modification of an existing monitoring system in terms of compactness, reliability and flexibility. In this paper, we designed UART and FIR filter in VHDL using Xilinx ISE software and verified using MODELSIM. Various working registers and all standard serial interface protocols are implemented in UART using Xilinx SpartanII Device, XC2S50.

VI. Acknowledgement

This work is supported in part by NASAN MEDICAL ELECTRONICS, PUNE. The authors would like to thank Mr.Vishal Kale, Robert Bosch, Bangalore, Dr.P.B.Mane Principal, AISSMS’s IOIT and Mr.H.P.Chaudhari, HOD for their constant encouragement and support. The authors are also very much thankful for anonymous reviewers and editor.

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VII. REFERENCES

[1].Allison L. Walters, “A Scaleable FIR Filter Implementation using 32-bit Floating- Point Complex Arithmetic on a FPGA Based Custom Computing Platform”,Proc. Of IEEE Symposium on FPGAs for Custom Computing Machines, 1998, Ca, USA, PP 333-334, 1998.

[2].K. C. Chang, “Digital System Design with VHDL and

Synthesis: An Integrated Approach”, Wiley, Paperback

[3].David J. Farrell, David M. Williams, “Implementation of

Digital Filters in Programmable Logic Devices”, Proc.

Of International Conference on Embedded Systems, San

Francisco, Spring, 2001.

[4]. [Online] Agatep, “Xilinx

Spartan II FIR filter Solution”, Xilinx application note

[5].Peter J. Ashenden, “The Designer’s Guide to VHDL”,

Morgan Kaufmann Publishers,2nd Edition,2002

[6].

Figure 9 Simulating waveform supporting experimentation of FIR.

/ Vandana V. Kale is currently working as Lecturer in Department of Instrumentation and Control Engineering, AISSMS’ Institute of Information Technology, Pune, affiliated to the University of Pune. She received her BE from S.G.G.S.I.E. & T., SRTMU, Nanded and M. Tech. fromCollege of Engineering, Pune (An Autonomous Institute of Government of Maharashtra). She has one year of experience in teaching undergraduate students. Her research interests are in the areas of VLSI and digital signal processing.
/ Atika A. Jainis currently working as Lecturer in the Department of Instrumentation and Control Engineering, AISSMS’ Institute of Information Technology, Pune, affiliated to the University of Pune. She received her BE from the RajasthanUniversity, Jaipur.She is working towards herM.Tech.at VIT, Pune. She has 4 years of experience in teaching undergraduate students. Her research interests are in the areas of VLSI, digital image processing and digital signal processing.
/ Amol D. Rahulkar is currently working as Assistant Professor in the Department of Instrumentation and Control Engineering, AISSMS’ Institute of Information Technology, Pune, affiliated to theUniversity of Pune. He is working towards his PhD at S.G.G.S.I.E. & T., SRTMU, Nanded. He received his B E from the same institute and M. Tech. from IIT, Kharagpur. He has seven years of experience in teaching undergraduate students. His research interests are in the areas of digital image processing, Biometrics, Wavelet transform and Reliability Engineering.