VELTECH MULTI TECH Dr. RANGARAJAN Dr. SAKUNTHALA ENGINEERING COLLEGE

VELTECH MULTI TECH Dr. RANGARAJAN Dr. SAKUNTHALA ENGINEERING COLLEGE

Accredited by NBA, New Delhi

An ISO 9001:2008 Certified Institution

(Owned by Vel Trust 1997)

Approved by AICTE, New Delhi NBA Accredited& Affiliated to Anna University Chennai-25

SYLLABUS

WEEKLY SCHEDULE

SEMESTER I 2013- 2014

I YEAR M.E VLSI DESIGN

TWO YEAR COURSE

# 60, Avadi - Alamathi Road, Chennai - 600 062.

Phone: 25017073 / 25017584

E-mail:

Website:

CONTENTS

S.NO / SUB. CODE / SUBJECT
1. / MA9217 /

APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS

2. / VL 9211 / DSP INTEGRATED CIRCUITS
3. / AP9212 / ADVANCED DIGITAL SYSTEM DESIGN
4. / VL9212 / VLSI DESIGN TECHNIQUES
5. / VL9213 / SOLID STATE DEVICE MODELING AND SIMULATION
6. / VL9256 / VLSI TECHNOLOGY
PRACTICAL
7. / VL9217 / VLSI DESIGN LAB I

VELTECH MULTITECH Dr.RANGARAJANDr.SAKUNTHALA ENGG. COLLEGE

DEPARTMENT OF ECE

M.E. VLSI DESIGN

WEEKLY SCHEDULE

SEM : I YEAR : I

ACADEMIC YEAR: 2013– 2014

S.No / WEEKS / DATE
FROM / TO
1 / WEEK1 / 11.09.13 / 14.09.13
2 / WEEK2 / 16.09.13 / 21.09.13
3 / WEEK3 / 23.09.13 / 28.09.13
4 / WEEK4 / 30.09.13 / 5.10.13
5 / WEEK5 / 7.10.13 / 12.10.13
6 / WEEK6 / 15.10.13 / 19.10.13
7 / WEEK7 / 21.10.13 / 26.10.13
8 / WEEK8 / 28.10.13 / 1.11.13
9 / WEEK9 / 4.11.13 / 9.11.13
10 / WEEK10 / 11.11.13 / 16.11.13
11 / WEEK11 / 18.11.13 / 23.11.13
12 / WEEK12 / 25.11.13 / 30.11.13
13 / WEEK13 / 2.12.13 / 7.12.13
14 / WEEK14 / 9.12.13 / 14.12.13

TEST SCHEDULE

CYCLE TEST - I

Sl.
NO / DATE / SUB.CODE / SUBJECT
1 / 21.10.13 / MA9217 /

APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS

2 / 22.10.13 / VL 9211 / DSP INTEGRATED CIRCUITS
3 / 23.10.13 / AP9212 / ADVANCED DIGITAL SYSTEM DESIGN
4 / 24.10.13 / VL9212 / VLSI DESIGN TECHNIQUES
5 / 25.10.13 / VL9213 / SOLID STATE DEVICE MODELING AND SIMULATION
6 / 26.10.13 / VL9256 / VLSI TECHNOLOGY

CYCLE TEST - II

Sl.
NO / DATE / SUB.CODE / SUBJECT
1 / 25.11.13 / MA9217 /

APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS

2 / 26.11.13 / VL 9211 / DSP INTEGRATED CIRCUITS
3 / 27.11.13 / AP9212 / ADVANCED DIGITAL SYSTEM DESIGN
4 / 28.11.13 / VL9212 / VLSI DESIGN TECHNIQUES
5 / 29.11.13 / VL9213 / SOLID STATE DEVICE MODELING AND SIMULATION
6 / 30.11.13 / VL9256 / VLSI TECHNOLOGY

MODEL EXAM - I

Sl.
NO / DATE / SUB.CODE / SUBJECT
1 / 16.12.13 / MA9217 /

APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS

2 / 17.12.13 / VL 9211 / DSP INTEGRATED CIRCUITS
3 / 18.12.13 / AP9212 / ADVANCED DIGITAL SYSTEM DESIGN
4 / 19.12.13 / VL9212 / VLSI DESIGN TECHNIQUES
5 / 20.12.13 / VL9213 / SOLID STATE DEVICE MODELING AND SIMULATION
6 / 21.12.13 / VL9256 / VLSI TECHNOLOGY

MA9217 APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS

UNITI FUZZY LOGIC

WEEK-1Classical logic – Multi valued logics.

WEEK-2Fuzzy propositions – Fuzzy quantifiers.

WEEK-3- UNIT TEST-1

UNITII MATRIX THEORY

WEEK-4Some important matrix factorizations – The Cholesky decomposition – QR factorization.

WEEK-5Singular value decomposition - Toeplitz matrices and some applications.

WEEK-6 UNIT TEST-2

UNITIII DIMENSIONAL RANDOM VARIABLES

WEEK-7Random variables - Probability function – moments – moment generating functions and their properties – Binomial, Poisson.

WEEK-8Geometric, Uniform, Exponential, Gamma and Normal distributions – Function of a Random Variable.

WEEK-9 UNIT TEST-3

UNITIV DYNAMIC PROGRAMMING

WEEK-10Dynamic programming – Principle of optimality.

WEEK11Forward and backward recursion – Applications of dynamic programming – Problem of dimensionality.

WEEK-12 UNIT TEST-4

WEEK-13 &14 UNITS-I to UNIT-IV REVISION

UNITV QUEUEING MODELS

WEEK-15Poisson Process – Markovian queues – Single and Multi-server Models

WEEK-16Little’s formula - Machine Interference Model – Steady State analysis – Self Service queue.

WEEK-17 MODEL EXAM THEORY

WEEK-18 MODEL EXAM PRACTICAL EXAMINATION

REFERENCES:

George J. Klir and Yuan, B., Fuzzy sets and fuzzy logic, Theory and applications, Prentice Hall of India Pvt. Ltd., 1997.
Moon, T.K., Sterling, W.C., Mathematical methods and algorithms for signal processing, Pearson Education, 2000.
Richard Johnson, Miller & Freund’s Probability and Statistics for Engineers,

7thEdition, Prentice – Hall of India, Private Ltd., New Delhi (2007).

Taha, H.A., Operations Research, An introduction, 7th edition, Pearson education editions, Asia, New Delhi, 2002.
Donald Gross and Carl M. Harris, Fundamentals of Queueing theory, 2nd edition, John Wiley and Sons, New York (1985).

VL 9211 DSPINTEGRATED CIRCUITS

UNIT I DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

WEEK-1Standard digital signal processors, Application specific IC’s for DSP, DSP systems, DSP system design.

WEEK-2Integrated circuit design. MOS transistors, MOS logic, VLSI process technologies, Trends in CMOS technologies.

WEEK-3- UNIT TEST-1

UNIT II DIGITAL SIGNAL PROCESSING

WEEK-4Digital signal processing, Sampling of analog signals, Selection of sample frequency, Signal- processing systems, Frequency response, Transfer functions.

WEEK-5Signal flow graphs, Filter structures, Adaptive DSP algorithms, DFT-The Discrete Fourier Transform, FFT-The Fast Fourier Transform Algorithm, Image coding, Discrete cosine transforms.

WEEK-6- UNIT TEST-2

UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

WEEK-7FIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Mapping of analog transfer functions, Mapping of analog filter structures, Multirate systems, Interpolation with an integer factor L

WEEK-8Sampling rate change with a ratio L/M, Multirate filters. Finite word length effects -Parasitic oscillations, Scaling of signal levels, Round-off noise, Measuring round-off noise, Coefficient sensitivity, Sensitivity and noise.

WEEK-9- UNIT TEST-3

UNITIVDSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

WEEK-10DSP system architectures, Standard DSP architecture, Ideal DSP architectures, Multiprocessors and multicomputers, Systolic and Wave front arrays

WEEK-11Shared memory architectures. Mapping of DSP algorithms onto hardware, Implementation based on complex PEs, Shared memory architecture with Bit – serial PEs.

WEEK-12- UNIT TEST-4

WEEK-13 &14 UNITS-I to UNIT-IV REVISION

UNITVARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN

WEEK-15Conventional number system, Redundant Number system, Residue Number System, Bit-parallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size.

WEEK-16Complex multipliers, Improved shift-accumulator. Layout of VLSI circuits, FFT processor, DCT processor and Interpolator as case studies. Cordic algorithm.

WEEK-17 MODEL EXAM THEORY

WEEK-18 MODEL EXAM PRACTICAL EXAMINATION

REFERENCES:

Lars Wanhammer, “DSP Integrated Circuits”, 1999 Academic press, New York.
A.V.Oppenheim et.al, “Discrete-time Signal Processing”, Pearson Education, 2000.
Emmanuel C. Ifeachor, Barrie W. Jervis, “Digital signal processing – A practical approach”, Second Edition, Pearson Education, Asia.
Keshab K.Parhi, “VLSI Digital Signal Processing Systems design and Implementation”, John Wiley & Sons, 1999.

AP9212 ADVANCED DIGITAL SYSTEM DESIGN

UNIT ISEQUENTIAL CIRCUIT DESIGN

WEEK-1Analysis of clocked synchronous sequential circuits and modeling- State diagram, state table, state table assignment.

WEEK-2Reduction-Design of synchronous sequential circuits-design of iterative circuits-ASM chart and realization using ASM.

WEEK-3 UNIT TEST-1

UNITII ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

WEEK-4Analysis of asynchronous sequential circuit – flow table reduction-races-state assignment-transition table and problems in transition table

WEEK-5 Design of asynchronous sequential circuit-Static, dynamic and essential hazards – data synchronizers – mixed operating mode asynchronous circuits – designing vending machine controller

WEEK-6 UNIT TEST-2

UNITIIIFAULT DIAGNOSIS AND TESTABILITY ALGORITHMS

WEEK-7Fault table method-path sensitization method – Boolean difference method-D algorithm -Tolerance techniques

WEEK-8The compact algorithm – Fault in PLA – Test generation-DFT schemes – Built in self test

WEEK-9 UNIT TEST-3

UNITIVSYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES

WEEK-10Programming logic device families – Designing a synchronous sequential circuit using PLA/PAL

WEEK-11Realization of finite state machine using PLD – FPGA – Xilinx FPGA-Xilinx 4000

WEEK-10 UNIT TEST-4

WEEK-13 &14 UNITS-I to UNIT-IV REVISION

UNITVSYSTEM DESIGN USING VHDL

WEEK-15VHDL operators – Arrays – concurrent and sequential statements – packages- Data flow – Behavioral – structural modeling – compilation and simulation of VHDL code –Test bench.

WEEK-16Realization of combinational and sequential circuits using HDL – Registers – counters – sequential machine – serial adder – Multiplier- Divider – Design of simple microprocessor.

WEEK-17 MODEL EXAM THEORY

WEEK-18 MODEL EXAM PRACTICAL EXAMINATION

REFERENCES:

1.Charles H.Roth Jr “Fundamentals of Logic Design” Thomson Learning 2004.

2.Dhanam Publications,2011 Nripendra N Biswas “Logic Design Theory” Prentice Hall of
India,2001

3.Parag K.Lala “Fault Tolerant and Fault Testable Hardware Design” B S Publications,2002

4. Parag K.Lala “Digital system Design using PLD” B S Publications,2003

5. Charles H Roth Jr.”Digital System Design using VHDL” Thomson learning, 2004

6. Douglas L.Perry “VHDL programming by Example” Tata McGraw.Hill – 2006

VL9212VLSI DESIGNTECHNIQUES

UNITIMOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

WEEK-1NMOS and PMOS transistors, Threshold voltage- Body effect- Design equations- Second order effects.

WEEK-2MOS models and small signal AC characteristics. Basic CMOS technology.

WEEK-3 UNIT TEST-1

UNITII INVERTERS AND LOGIC GATES

WEEK-4NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient characteristics , switching times, Super buffers.

WEEK-5Driving large capacitance loads, CMOS logic structures , Transmission gates, Static CMOS design, dynamic CMOS design.

WEEK-6 UNIT TEST-2

UNITIIICIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION

WEEK-7Resistance estimation, Capacitance estimation, Inductance, switching characteristics

WEEK-8transistor sizing, power dissipation and design margining. Charge sharing .Scaling.

WEEK-9 UNIT TEST-3

UNITIV SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL PHYSICAL DESIGN

WEEK-10Multiplexers, Decoders, comparators, priority encoders, Shift registers. Arithmetic circuits – Ripple carry adders, Carry look ahead adders, High-speed adders.

WEEK-11Multipliers. Physical design – Delay modelling ,cross talk, floor planning, power distribution. Clock distribution. Basics of CMOS testing.

WEEK-12 UNIT TEST-4

WEEK-13 &14 UNITS-I to UNIT-IV REVISION

UNITVVERILOG HARDWARE DESCRIPTION LANGUAGE

WEEK-15Overview of digital design with Verilog HDL, hierarchical modelling concepts, modules and port definitions

WEEK-16Gate level modelling, data flow modelling, behavioral modelling, task & functions, Test Bench.

WEEK-17 MODEL EXAM THEORY

WEEK-18 MODEL EXAM PRACTICAL EXAMINATION

REFERENCES

1.Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson
Education ASIA, 2nd edition, 2000.

2. John P.Uyemura “Introduction to VLSI Circuits and Systems”, John Wiley & Sons, Inc.,
2002.

3. Samir Palnitkar, “Verilog HDL”, Pearson Education, 2nd Edition, 2004.

4.Eugene D.Fabricius, Introduction to VLSI Design McGraw Hill International Editions, 1990.

5.J.Bhasker, B.S.Publications, “A Verilog HDL Primer”, 2nd Edition, 2001.

6..Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.

7.Wayne Wolf “Modern VLSI Design System on chip. Pearson Education.2002.

VL9213SOLIDSTATE DEVICE MODELING AND SIMULATION

UNITIMOSFET DEVICE PHYSICS

WEEK-1 MOSFET capacitor, Basic operation, Basic modeling,Advanced MOSFET modeling, RF modeling of MOS transistors, Equivalent circuit representation of MOS transistor, High frequency behavior of MOS transistor

WEEK-2 and A.C small signal modeling, model parameter extraction, modeling parasitic BJT, Resistors, Capacitors, Inductors.

WEEK-3 UNIT TEST-1

UNITII NOISE MODELING

WEEK-4Noise sources in MOSFET, Flicker noise modeling, Thermal noise modeling, model for accurate distortion analysis

WEEK-5, nonlinearities in CMOS devices and modeling, calculation of distortion in analog CMOS circuits

WEEK-6 UNIT TEST-2

UNITIII BSIM4 MOSFET MODELING

WEEK-7 Gate dielectric model, Enhanced model for effective DC and AC channel length and width, Threshold voltage model, Channel charge model, mobility model, Source/drain resistance model, I-V model.

WEEK-8Gate tunneling current model, substrate current models, Capacitance models, High speed model, RF model, noise model, junction diode models, Layout-dependent parasitics model

WEEK-9 UNIT TEST-3

UNITIV OTHER MOSFET MODELS

WEEK-10The EKV model, model features, long channel drain current model, modeling second order effects of the drain current

WEEK-11modeling of charge storage effects, Non-quasi-static modeling, noise model temperature effects, MOS model 9, MOSAI model)

WEEK-12 UNIT TEST-4

WEEK-13 &14 UNITS-I to UNIT-IV REVISION

UNITVMODELLING OF PROCESS VARIATION AND QUALITY ASSURANCE

WEEK-15Influence of process variation, modeling of device mismatch for Analog/RF Applications

WEEK-16Benchmark circuits for quality assurance, Automation of the tests

REFERENCES:

1.Benchmark circuits for quality assurance, Automation of the tests

VL9256 VLSI TECHNOLOGY

UNITICRYSTAL GROWTH, WAFER PREPARATION, EPITAXY AND

OXIDATION

WEEK-1Electronic Grade Silicon, Czochralski crystal growing, Silicon Shaping, processing consideration, Vapor phase Epitaxy, Molecular Beam Epitaxy, Silicon on Insulators, Epitaxial Evaluation, Growth Mechanism and kinetics.

WEEK-2Thin Oxides, Oxidation Techniques and Systems, Oxide properties, Redistribution of Dopants at interface, Oxidation of Poly Silicon, Oxidation induced Defects

WEEK-3 UNIT TEST-1

UNITIILITHOGRAPHY AND RELATIVE PLASMA ETCHING

WEEK-4Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography, Plasma properties

WEEK-5 Feature Size control and Anisotropic Etch mechanism, relative Plasma Etching techniques and Equipments.

WEEK-6 UNIT TEST-2

UNITIII DEPOSITION, DIFFUSION, ION IMPLEMENTATION AND

METALISATION

WEEK-7Deposition process, Polysilicon, plasma assisted Deposition, Models of Diffusion in Solids, Flick’s one dimensional Diffusion Equation – Atomic Diffusion Mechanism

WEEK-8Measurement techniques - Range theory- Implant equipment. Annealing Shallow junction – High energy implantation – Physical vapour deposition – Patterning.

WEEK-9 UNIT TEST-3

UNITIV PROCESS SIMULATION AND VLSI PROCESS INTEGRATION

WEEK-10Ion implantation – Diffusion and oxidation – Epitaxy – Lithography – Etching and Deposition- NMOS IC Technology

WEEK-11CMOS IC Technology – MOS Memory IC technology - Bipolar IC Technology – IC Fabrication.

WEEK-12 UNIT TEST-4

WEEK-13 &14 UNITS-I to UNIT-IV REVISION

UNITVASSEMBLY TECHNIQUES AND PACKAGING OF VLSI DEVICES

WEEK-15Analytical Beams – Beams Specimen interactions - Chemical methods – Package types – banking design consideration

WEEK-16 VLSI assembly technology – Package fabrication technology.

WEEK-17 MODEL EXAM THEORY

WEEK-18 MODEL EXAM PRACTICAL EXAMINATION

REFERENCES:

1.S.M.Sze, “VLSI Technology”, Mc.Graw.Hill Second Edition. 2002.

2. Douglas A. Pucknell and Kamran Eshraghian, “ Basic VLSI Design”, Prentice Hall

India 2003.

3. Amar Mukherjee, “Introduction to NMOS and CMOS VLSI System design Prentice Hall India.2000.

4. Wayne Wolf ,”Modern VLSI Design”, Prentice Hall India.1998.

VL9217 VLSIDESIGN LAB I

LISTOFEXPERIMENTS:

Modeling of Sequential Digital system using VHDL.
Modeling of Sequential Digital system using Verilog.
Design and Implementation of ALU using FPGA.
Simulation of NMOS and CMOS circuits using SPICE.
Modeling of MOSFET using C.
Implementation of FFT, Digital Filters in DSP Processor.
Implementation of DSP algorithms using software package.
Implementation of MAC Unit using FPGA.