EC2354 VLSI DESIGN
Unit III QUESTION BANK
PREPARED BY

V. VAITHIANATHAN, AP/ECE, SSNCE

Part – A

  1. What is meant by bubble pushing?
  2. Draw the logic gate for AOI22 compound gate.
  3. Draw the logic gate for AOI322 compound gate.
  4. Draw the logic gate for OAI22 compound gate.
  5. What is meant by input ordering delay effect?
  6. What are asymmetric gates?
  7. What is skewed gate? State its types.
  8. What is the best P/N ratio for logic gates?
  9. Why multiple threshold voltages are required?
  10. What is Pseudo-nMOS? State its merits and demerits.
  11. Draw AND gate using Pseudo-nMOS.
  12. Design a K-input AND gate with DeMorgan's Law using static CMOS inverters followed by a K-input pseudo-nMOS NOR.
  13. What is Ganged CMOS?
  14. What is Source Follower Pull-up Logic (SFPL)?
  15. Draw a 4-input NOR gate using Source Follower Pull-up Logic (SFPL).
  16. Draw the structure for generalized footed and unfooted dynamic gates.
  17. Draw the footedand unfooted dynamic inverter.
  18. Draw the footedand unfooted dynamic NAND2.
  19. Draw the footedand unfooted dynamic NOR2.
  20. What is monotonicity problem? How do you avoid it?
  21. What is domino logic?
  22. What are Keepers? Why are they required?
  23. Draw the circuit of differential keeper.
  24. What is burn-in conditional keeper?
  25. What is meant by precharging? How does it overcome charge sharing problem?
  26. What are NP and Zipper Domino?
  27. What are pass transistors?
  28. What is meant by transmission gate?
  29. Implement AND gate transmission gate.
  30. What are poor zeros and poor ones? How can they be avoided?
  31. What is Complementary Pass Transistor Logic (CPL)?
  32. What are the different sources of power consumption?
  33. Define activity factor.
  34. Sketch a 3-input CVSL OR/NOR gate.
  35. Sketch a 3-input dual-rail domino OR/NOR gate.
  36. Design a fast-pulsed latch.
  37. Define the following
  38. Logic Propagation Delay (2)
  39. Logic Contamination Delay (2)
  40. Latch/Flop Clock-to- Q Propagation Delay (2)
  41. Latch/Flop Clock-to- Q Contamination Delay (2)
  42. Latch D-to-Q Propagation Delay (2)
  43. Latch D-to-Q Contamination Delay (2)
  44. Latch/Flop Setup Time (2)
  45. Latch/Flop Hold Time (2)
  46. What are max-delay timing constraints?
  47. What is meant by setup time failure or max-delay failure?
  48. What are min-delay timing constraints?
  49. What is meant by Time Borrowing?
  50. Define clock skew.
  51. What is meant by C2MOS latch?
  52. List out all the issues that designers must address when selecting a sequencing element methodology.
  53. What are precharge and evaluation phases?
  54. What are Skew-tolerant Domino Circuits?
  55. What is meant by Opportunistic Time Borrowing?
  56. Define metastability.
  57. Define MTBF.
  58. What is arbiter?

Part – B

  1. With an example, explain how bubble pushing is used to convert ANDs and ORs to NANDs and NORs.(8)
  2. Calculate the minimum delay, in τ, to compute F = AB + CD using the circuits from figure (a) and (b). Each input can present a maximum of 20 λ. of transistor width. The output must drive a load equivalent to 100 λ, of transistor width. Choose transistor sizes to achieve this delay. (8)

  1. Design a circuit to compute F = AB+ CD using NANDs and NORs. (8)
  2. Design a static CMOS circuit to compute F= (A + B)(C + D) with least delay. Each input can present a maximum of 30 λ of transistor width. The output must drive a load equivalent to 500 λ of transistor width. Choose transistor sizes to achieve least delay and estimate this delay in τ. (8)
  3. Sketch a schematic for a 12-input OR gate built from NANDs and NORs of no more than 3 inputs each. (8)
  4. Explain in detail different types of static CMOS circuits. (16)
  5. Explain in detail different types ofRatioed Circuits (8)
  6. Prove that the P/N ratio that gives lowest average delay in a logic gate is the square root of the ratio that gives equal rise and fall delays. (8)
  7. Explain in detail Cascode Voltage Switch Logic (CVSL ). (8)
  8. Explain in detail different types of Domino Logic. (16)
  9. Explain in detail different types of Pass Transistor Logic. (16)
  10. Explain in detail low power logic design. (8)
  11. Compare different types of circuit families. (16)
  12. Discuss in detail different types of static sequencing methods. (16)
  13. Discuss in detail max-delay timing constraints and min-delay timing constraints. (8)
  14. Explain in detail Time Borrowing (8)
  15. Discuss in detail various methods of Circuit Design of Latches. (16)
  16. Discuss in detail various methods of Circuit Design of Flip-flops. (16)
  17. Explain different types of transparent latches. (8)
  18. Discuss in detail various issues that designers must address when selecting a sequencing element methodology. (8)
  19. Discuss in detail various tradeoffs offered by flip-flops, pulsed latches, and transparent latches in sequencing overhead, skew tolerance, and simplicity. (8)
  20. Discuss in detail Sequencing Dynamic Circuits. (16)
  21. Discuss in detail the operation of synchronizer.

EC2354 VLSI Design Question Bank – Unit III: Prepared By V. Vaithianathan, AP/ECE, SSNCE