Using Buses in Xilinx Foundation 2

Xilinx 3.1i Bus Tutorial:(Original Idea by Greg Helm(GTA 2001) for Xilinx 2.1i tutorial)

Modified and Edited by Karthikeyan Balasundaram & Sridhar Ramachandran (Dec 2002)

This tutorial will cover the use of buses.

What is a bus?

A bus is merely a grouping of individual signals.

Buses are used to add clarity to a schematic drawing and also for convenience. It would not be very fun to draw and label every wire individually for a 128-bit bus!

Often a bus is a set of signals that will represent a numeric value.

Typically in the foundation tools, buses are specified in the following way.

Name[msb:lsb]

For example SUM[7:0] would be an eight bit bus named SUM. The ‘most significant bit’ of this bus would be the signal SUM7 and the ‘least significant bit’ would be SUM0

The following illustration shows a bus and all of the signals broken out from that bus.

The bus is represented by the thick line on the screen. To draw a bus select the “Draw Buses” button on the toolbar.

When drawing a bus, you will find it best to begin a bus at the ‘far end’ of the bus. This is because when you double click to end a bus that is where the hierarchical port connector will be placed (assuming that you do want a hierarchical port, and the bus does not end on a symbol pin).

When you double click to end a bus the following window will pop-up.

In the “Name” field, type the bus name.

In the “Range” fields you can specify the MSB and LSB values of your bus (either type the value directly or use the up/down arrows to choose a value).

Under “Terminal Marker”, you can specify the hierarchical port type…

NONE – places no port connector on the bus. Use this if the bus does not need to traverse a level of hierarchy. Only a label will be placed next to the bus.

INPUT – places an input port connector and label on the bus

OUTPUT – places an output port connector and label on the bus

BDIRECTIONAL – places an bidirectional port connector and label on the bus

You can also choose “Bus End” to terminate a bus with no port connector and no label

SUM[7:0] – Indicates the range of the bus is 8-bits

SUM 0 - Indicates the LSB bit of 8-bit SUM input

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SUM 7 - Indicates the MSB bit of 8-bit SUM input

To connect a wire to a bus, either use the “Draw Wires” tool and any wire that you draw that ends on a bus line will automatically be connected, or use the “Bus Taps” tool, which is briefly discussed later.

Remember to label any wire that is connected to a bus. Since a bus is a collection of wires, the tools have no way to know which wire you want unless you label it.

Also if you double click on a bus that does not contain a port connector you will see the following

window…

This window gives you the same options as discussed previously, and also gives you the option to choose the shape of your “bus taps”. A bus tap is just a connection of a single wire onto the bus. Bus taps are used when you need to use the single wires to connect to symbols, or when combining individual signals into a bus.

It doesn’t matter what shape bus tap you choose – it is just a matter of personal preference.

An important thing to keep in mind, is that all bus segments should be labeled. This is necessary so that the schematic tools can determine which signals are present on any given bus segment.

Here is an example of generating a bus from several different sources….

The same general idea can be used to split up a bus into bus slices (sub-buses) and individual signals.

The BUF symbol is used to change the name of a wire. In the example above, one wire is changed from the name INSIGNAL to RESULT15. Another wire is changed from the name GND to RESULT12. In the Xilinx tools, the BUF does not introduce delay, its main purpose is labeling convenience.

Another handy tool to experiment with is the “Bus Tap” tool.

This can be used to draw bus taps and wired from a symbol pin to a vertically drawn bus line.

To use the bus tap tool, Click the bus tap button. Next click the bus that you wish to connect to. Then click on the symbol pin. A wire will then be drawn from the symbol pin to the bus. The wire will also be automatically labeled starting with the MSB. Feel free to experiment with this tool.

Finally, when choosing a bus name, do not choose a name that ends with a numeric character.

For example … BUS1[15:0]

If you do this, then the individual signal names will be BUS10 (lsb), BUS11, BUS12, BUS13, … BUS115 (msb). This may give you unexpected/undesired results.

Buses and Simulation

When simulating, buses are selected and viewed just like any other signal. However, there are a few special things you can do that you should be aware of

DISPLAY

When looking at a bus in the simulation display, the default is to display the value of the bus as a hexadecimal number. Here we see a simulation of the circuit drawn earlier to generate the RESULT[15:0] bus.

If you are not happy with a hexadecimal display, then you can choose your radix. To do this, first highlight the bus then go to the menu bar and click “Signal – Bus --- …

Display Binary

Display Octal

Display Decimal

Display Hexadecimal

If you wish to display the individual bits of the bus or place “Stimulators” on individual signals then first you must “flatten” the bus. Flattening a bus changes the display so that every individual bus line is visible. To do this highlight the bus then goes to the menu bar and click “Signal – Bus --- Flatten”. Refer to the above screenshot.

To recreate a bus from individual signals, select all of the signals of interest (to select multiple signals hold down the Ctrl or Shift keywhile selecting). Once they are selected, go to the menu bar and click “Signal – Bus --- Combine”.

Note: Signals with unrelated names can be combined into a “Bus” for display in the Simulator tool.

If you are suspect that the Simulation tool is displaying your bus in the reverse order, meaning that the MSB and LSB are swapped, as well as every signal in between, then you can click “Signal – Bus --- Change Direction” to correct the display.

A last note (for now) about simulating with buses is... If you wish to type in a numeric value for bus that is an input to your simulation then click the “Logical States” button on the toolbar. This will give you the following window…

To set a bus value. Highlight the bus of interest. Type the hexadecimal bus value into the “BusState” field, and then click the “Bus” button. This will set the bus to your specified value.

“StimulatorState Selection” can also be used on individual signals if you wish to set a signal always “low” or always “high”

Some more examples of using Buses:

1)To run a 4-bit counter circuit

To assign values for the bus

# Select the bus input

# Go to logic states

# Using bus state provision assign values to the bus

# then click on the Bus to enable the assigning of values

# similarly, to assign values to the single bit input using logic states, use low or high for assigning

0 or 1

To assign clock signal, we do the following steps:

# Go to select simulators

# Click the “Formula”

# We have provision to generate 4 clock signals, but since we use only synchronous devices, only usage of single clock is sufficient

# Then click Accept to assign the clock to C1

# then click close, u could see C1 is active high

# then assigns C1 to the input name clk

# Click close, we have successfully generated the clock signal and simulated the circuit

Busses are a very convenient and useful schematic element.

They save you from drawing and labeling many individual wires. You also don’t need as many port connectors and I/O pins on your hierarchical symbols.

They result in cleaner, easier to read schematics and simulations.

It is important to become familiar with using busses. They are not difficult to use as long as you name them wisely and as long as you name every segment of a bus - especially when you are taking a slice of a bus. Also name any wire that is a tap from a bus.

Another Note:

Make sure that the width (number of signals) of a bus slice matches the width of any I/O pin on a symbol that it connects to. Width mismatches will cause you unexpected problems.

If you have any problems, do not hesitate to ask your TA