TX/RX with interrupts from clock_pt1
//******************************************************************************
// CC430F513x Demo - USCI_A0, UART 9600 Full-Duplex Transceiver, 32K ACLK
//
// Description: USCI_A0 communicates continuously as fast as possible
// full-duplex with another device. Normal mode is LPM3, with activity only
// during RX and TX ISR's. The TX ISR indicates the UART is ready to send
// another character. The RX ISR indicates the UART has received a character.
// At 9600 baud, a full character is tranceived ~1ms.
// The levels on P1.4/5 are TX'ed. RX'ed value is displayed on P1.0/1.
// ACLK = BRCLK = LFXT1 = 32768, MCLK = SMCLK = DCO~ 1048k
// Baud rate divider with 32768hz XTAL @9600 = 32768Hz/9600 = 3.41 (0003h 4Ah)
//
//
// CC430F5137 CC430F5137
// ------
// /|\ | XIN|- /|\ | XIN|-
// | | | 32KHz | | | 32KHz
// --|RST XOUT|- --|RST XOUT|-
// | | | |
// | | | |
// | | | |
// ->|P1.4 | | P1.0|-> LED
// ->|P1.5 | | P1.1|-> LED
// LED <-|P1.0 | | P1.4|<-
// LED <-|P1.1 | | P1.5|<-
// | UCA0TXD/P2.7|------>|P2.6/UCA0RXD |
// | | 9600 | |
// | UCA0RXD/P2.6|<------|P2.7/UCA0TXD |
//
//
// M Morales
// Texas Instruments Inc.
// April 2009
// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//******************************************************************************
#include"cc430x513x.h"
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
P5SEL |= 0x03; // Enable XT1 pins
do
{
UCSCTL7 &= ~(XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
__delay_cycles(100000); // Delay for Osc to stabilize
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
P1OUT = 0x000; // P1.0/1 setup for LED output
P1DIR |= BIT0+BIT1; //
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP6 = PM_UCA0RXD; // Map UCA0RXD output to P2.6
P2MAP7 = PM_UCA0TXD; // Map UCA0TXD output to P2.7
PMAPPWD = 0; // Lock port mapping registers
P2DIR |= BIT7; // Set P2.7 as TX output
P2SEL |= BIT6 + BIT7; // Select P2.6 & P2.7 to UART function
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_1; // CLK = ACLK
UCA0BR0 = 0x03; // 32k/9600 - 3.41
UCA0BR1 = 0x00; //
UCA0MCTL = 0x06; // Modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCTXIE + UCRXIE; // Enable USCI_A0 TX/RX interrupt
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3 w/ interrupts enabled
__no_operation(); // For debugger
}
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
unsignedchar tx_char;
switch(__even_in_range(UCA0IV,4))
{
case 0: break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
P1OUT = UCA0RXBUF; // RXBUF1 to TXBUF1
break;
case 4: // Vector 4 - TXIFG
__delay_cycles(5000); // Add small gap between TX'ed bytes
tx_char = P1IN;
tx_char = tx_char > 4;
UCA0TXBUF = tx_char; // Transmit character
break;
default: break;
}
}
TX/RX with interrupts from clock_pt2
//******************************************************************************
// CC430F513x Demo - USCI_A0, SPI 3-Wire Master Incremented Data
//
// Description: SPI master talks to SPI slave using 3-wire mode. Incrementing
// data is sent by the master starting at 0x01. Received data is expected to
// be same as the previous transmission. USCI RX ISR is used to handle
// communication with the CPU, normally in LPM0. If high, P1.0 indicates
// valid data reception. Because all execution after LPM0 is in ISRs,
// initialization waits for DCO to stabilize against ACLK.
// ACLK = ~32.768kHz, MCLK = SMCLK = DCO ~ 1048kHz. BRCLK = SMCLK/2
//
// Use with SPI Slave Data Echo code example. If slave is in debug mode, P1.2
// slave reset signal conflicts with slave's JTAG; to work around, use IAR's
// "Release JTAG on Go" on slave device. If breakpoints are set in
// slave RX ISR, master must stopped also to avoid overrunning slave
// RXBUF.
//
// CC430F5137
// ------
// /|\| |
// | | |
// --|RST P1.0|-> LED
// | |
// | P2.0|-> Data Out (UCA0SIMO)
// | |
// | P2.2|<- Data In (UCA0SOMI)
// | |
// Slave reset <-|P1.2 P2.4|-> Serial Clock Out (UCA0CLK)
//
//
// M Morales
// Texas Instruments Inc.
// April 2009
// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//******************************************************************************
#include"cc430x513x.h"
unsignedchar MST_Data,SLV_Data;
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP0 = PM_UCA0SIMO; // Map UCA0SIMO output to P2.0
P2MAP2 = PM_UCA0SOMI; // Map UCA0SOMI output to P2.2
P2MAP4 = PM_UCA0CLK; // Map UCA0CLK output to P2.4
PMAPPWD = 0; // Lock port mapping registers
P1OUT |= BIT2; // Set P1.0 for LED
// Set P1.2 for slave reset
P1DIR |= BIT2 + BIT0; // Set P1.0, P1.2 to output direction
P2DIR |= BIT0 + BIT2 + BIT4; // ACLK, MCLK, SMCLK set out to pins
P2SEL |= BIT0 + BIT2 + BIT4; // P2.0,2,4 for debugging purposes.
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 0x02; // /2
UCA0BR1 = 0; //
UCA0MCTL = 0; // No modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
P1OUT &= ~0x02; // Now with SPI signals initialized,
P1OUT |= 0x02; // reset slave
__delay_cycles(100); // Wait for slave to initialize
MST_Data = 0x01; // Initialize data values
SLV_Data = 0x00; //
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = MST_Data; // Transmit first character
__bis_SR_register(LPM0_bits + GIE); // CPU off, enable interrupts
}
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
case 0: break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
if (UCA0RXBUF==SLV_Data) // Test for correct character RX'd
P1OUT |= 0x01; // If correct, light LED
else
P1OUT &= ~0x01; // If incorrect, clear LED
MST_Data++; // Increment data
SLV_Data++;
UCA0TXBUF = MST_Data; // Send next value
__delay_cycles(40); // Add time between transmissions to
// make sure slave can process information
break;
case 4: break; // Vector 4 - TXIFG
default: break;
}
}
TX Receive
//******************************************************************************
// CC430F513x Demo - USCI_A0, 115200 UART Echo ISR, DCO SMCLK
//
// Description: Echo a received character, RX ISR used. Normal mode is LPM0.
// USCI_A0 RX interrupt triggers TX Echo.
// Baud rate divider with 1048576hz = 1048576/115200 = ~9.1 (009h|01h)
// ACLK = REFO = ~32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
// See User Guide for baud rate divider table
//
// CC430F5137
// ------
// /|\| |
// | | |
// --|RST |
// | |
// | P2.7/UCA0TXD|------>
// | | 115200 - 8N1
// | P2.6/UCA0RXD|<------
//
// M Morales
// Texas Instruments Inc.
// April 2009
// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//******************************************************************************
#include"cc430x513x.h"
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP6 = PM_UCA0RXD; // Map UCA0RXD output to P2.6
P2MAP7 = PM_UCA0TXD; // Map UCA0TXD output to P2.7
PMAPPWD = 0; // Lock port mapping registers
P2DIR |= BIT7; // Set P2.7 as TX output
P2SEL |= BIT6 + BIT7; // Select P2.6 & P2.7 to UART function
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 9; // 1MHz 115200 (see User's Guide)
UCA0BR1 = 0; // 1MHz 115200
UCA0MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
__no_operation(); // For debugger
}
// Echo back RXed character, confirm TX buffer is ready first
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
Transmit RX
//******************************************************************************
// CC430F513x Demo - USCI_A0, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz ACLK
//
// Description: Echo a received character, RX ISR used. Normal mode is LPM3,
// USCI_A0 RX interrupt triggers TX Echo.
// ACLK = REFO = 32768Hz, MCLK = SMCLK = DCO ~1.045MHz
// Baud rate divider with 32768Hz XTAL @9600 = 32768Hz/9600 = 3.41
// See User Guide for baud rate divider table
//
// CC430F5137
// ------
// /|\| |
// | | |
// --|RST |
// | |
// | P2.7/UCA0TXD|------>
// | | 9600 - 8N1
// | P2.6/UCA0RXD|<------
//
// M Morales
// Texas Instruments Inc.
// April 2009
// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//******************************************************************************
#include"cc430x513x.h"
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP6 = PM_UCA0RXD; // Map UCA0RXD output to P2.6
P2MAP7 = PM_UCA0TXD; // Map UCA0TXD output to P2.7
PMAPPWD = 0; // Lock port mapping registers
P2DIR |= BIT7; // Set P2.7 as TX output
P2SEL |= BIT6 + BIT7; // Select P2.6 & P2.7 to UART function
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_1; // CLK = ACLK
UCA0BR0 = 0x03; // 32kHz/9600=3.41 (see User's Guide)
UCA0BR1 = 0x00; //
UCA0MCTL = UCBRS_3+UCBRF_0; // Modulation UCBRSx=3, UCBRFx=0
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, interrupts enabled
__no_operation(); // For debugger
}
// Echo back RXed character, confirm TX buffer is ready first
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}