This Month S Theme: Prototyping with Fpgas

FPGA Developer 9/05 – draft4/9/20191

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FPGA Developer

This Month’s Theme: Prototyping with FPGAs

Chip Design magazine – Inc. – 15, 2005

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Welcome to the September edition ofFPGA Developer. This e-newsletter complements Chip Design magazine by providing the latest FPGA and Structured ASIC news, opinions from industry experts, and timely technology articles. See below for subscribe andunsubscribe options.

Today's Table of Contents:

0.Editor’s Note –Taking an "Extra Step" to Save Time

1. ASIC Prototyping with FPGAs: Blessing or Curse?

2. Choosing the Right Silicon Technology

3.4 Million-Gate Radiation-Tolerant Device for Space Designs

4.Low Profile Socket Simplifies FPGA Prototyping in Space Constrained Applications

5.Software Development Environment Available for New Processor Families

6.Tunable Downconverter IP Core Boosts Channel Density for Military Radios and Commercial Wireless

7.Strategic Partnership Targets High-Performance Computing Markets

8. Collaboration to Make Reconfigurable Computing Easier to Programme

9.In-Depth Coverage Links

Structured and Platform ASIC Architectures Mandate Custom Physical Synthesis Solutions

Advanced FPGA Technology for In-System Verification

10. Online FPGA Resources

11. New Book

ASIC and FPGA Verification: A Guide to Component Modeling

12. Happenings

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0. Editor’s Note

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Taking an "Extra Step" to Save Time

By Jim Kobylecky, Editor

Why are so many ASIC designers adding the "extra step" of using FPGAs to prototype their ASIC systems? As FPGAs become faster and more powerful, they can stand in for ASICs even in more complex designs. Prototyping with an FPGA allows designers to explore architectural choices. Prototyping also allows engineers to verify hardware, firmware, and software functionality much earlier in the design, finding and solving problemsbefore they commit to silicon. It enables them to "step around"traditional bottlenecks and relieve some of the time-to-market pressures.

In this issue of FPGA Developer, we'll focuson how prototyping with FPGAs can help your ASIC design go further, faster, and for less. We’ll also cover how designers can use the programmable nature of FPGAs and Structured ASICs to effectively explore pre-silicon architectural trade-offs. But we'll also consider some the barriers that limit the efficiency of both these approaches. We'lllookat what toolmakers are doing to cross those barriers.

Our exclusive Viewpoints examine FPGA and Platform-ASIC prototyping from both the hardware and the software perspectives. In our In-Depth links you can explorean alternative Structured-ASIC approach and consider of the whole question of FPGAs versus ASICs. As always, you'll also find the latest FPGA and S-ASIC news and events.

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1.Viewpoint – Exclusive

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ASIC Prototyping with FPGAs: Blessing or Curse?

By Juergen Jaeger, Director of Marketing, Design Creation and Synthesis Division, Mentor Graphics ( and more ASIC designers consider using prototyping in FPGAs as a way to reduce risk and verify design functionality before committing to silicon. But where there is smoke, there is fire! On one hand, using FPGAs for ASIC prototyping is looked upon as a veritable nuisance and an additional design step. For many designs, however, it may be the only way to ensure the success of a tough ASIC project.

ASIC and SoC development will always be a risky and expensive business. Therefore, as programmable logic devices get larger and more versatile, they present increasingly attractive options not only for replacing ASICs in certain cases, but also for prototyping ASICs. Today’s devices now offer core performance in the hundreds of MHz range and densities in the millions of gates, enabling more ASIC designs to be prototyped on FPGAs for verification purposes. Companies benefit via the ability to:

• perform in-system verification techniques to identify and fix functional design errors
• significantly reduce technical risk
• evaluate hardware/software architectural tradeoffs in actual hardware, instead of at higher abstraction levels
• demonstrate working technology to customers before going into production

Using an FPGA to prototype ASIC functionality thus eases the time bottleneck created by shrinking market windows and reduces the need for other more expensive and time consuming methods to functionally verify SoC designs.

So, what’s Different for Prototyping?

The obvious differences lie in both the starting point and the end purpose. FPGA designs that are intended to be used in the end product basically start with a clean slate. The prototyping flow typically starts with an existing ASIC design. The designer’s sole purpose in mind is to verify that the ASIC works as intended, using the FPGA as a validation platform upon which she/he can make incremental changes on the way to achieving design closure.

A design team must consider different engineering needs in the prototyping world, including:

• Smooth and seamless transition between ASIC and FPGA realms
• Confidence in the tools, such that functionality is perfectly preserved
• Ability to use and automatically handle popular ASIC design constructs, like gated clocks
• Ability to use familiar ASIC flows, including Synopsys Design Constraints (SDC) format
• Wide language coverage (Verilog 2001, VHDL, SystemVerilog)
• In-depth analysis, cross-probing, and incremental design capabilities

As FPGAs continue to narrow the performance, density and cost gaps with ASICs, the design flows used for programmable logic start to resemble those used in ASICs, where design creation and synthesis is closely linked to verification. FPGA prototyping is done during the verification stage when the design is still in flux, which mandates the use of increasingly convergent synthesis and verification methodologies. And since the key purpose of ASIC prototyping using FPGAs is to ease the verification bottleneck, design tools that offer innovative analysis and incremental techniques are needed to accelerate system design and to take advantage of the programmable nature of FPGAs for in-system verification.

Upfront Analysis, Incremental Changes

Due to the higher silicon capacity and complexity typical involved in prototyping situations, the penalties associated with discovering and rectifying defects during later design stages can be severe. It is very important that FPGA design tools today deliver optimal design analysis capabilities to help raise the level of confidence that all the required features and functionality are fully realized in the prototype. FPGA synthesis tools used in prototyping must do more than just generate a technology-mapped netlist. They must provide more insight into the design at every stage in the cycle, by leveraging powerful ASIC-quality static timing analysis and extensive cross-probing capabilities to help designers quickly and easily identify potential problem areas such as clock domain crossings, memory initialization, etc.

It is also imperative for designers to do more timing and performance analysis up front. Design teams cannot wait until they have a working FPGA prototype to find out whether or not the chosen arbitration scheme is able to keep up with incoming traffic. Early discovery of throughput issues requires performing in-depth analysis throughout the synthesis process. Similarly, before burning cycles trying to meet timing constraints in place and route, designers must ensure that all constraints are complete. Early discovery of timing issues also requires analysis of constraint coverage during synthesis.

An essential weapon in any prototyping toolkit is an interactive synthesis and analysis environment that goes all the way from RTL to physical implementation. Interactive synthesis techniques provide guidance to the designer, allowing “what-if” explorations earlier in the design cycle. A robust synthesis environment also allows various design representations: high-level operators, architecture-specific technology cells, etc. Taking advantage of interactive synthesis capabilities provides an earlier understanding of the nature of the design and whether it will (or perhaps will not) meet specifications.

Also, since FPGA devices used in prototyping are bigger and more complex by their very nature, they drive the need for FPGA development tools that promote multiple design approaches: top-down, bottom-up and incremental.Incremental capabilities are an especially critical differentiator here, since prototyping is essentially done in tandem with the verification process. This implies that the design is always in flux, so the designer must have access to an efficient method by which to accelerate the time taken to re-implement design modifications into the prototype. This ability to adroitly make quick and incremental local changes (while locking down other pre-verified functional parts of the design in the FPGA) dramatically speeds up iterations and ensures prototyping success.

Using FPGAs for ASIC prototyping helps designers to verify hardware, firmware and application software design functionality before committing to first silicon. To be successful, however, the FPGA design software needs to provide the right mix of automation and user control, while maintaining flexibility. Design teams must now leverage the innovative timing analysis, incremental design and cross-probing capabilities offered in today’s FPGA synthesis tools to fully realize the promised benefits of prototyping, and thus ensure that their ASIC designs will ultimately work as intended.

Comments about this article? You may contact the author – Juergen Jaeger – at: . Or you may share you thoughts with other readers by contacting the editor at: .

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2. Viewpoint – Exclusive

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Choosing the Right Silicon Technology

Michael Sydow, Chief Operating Officer, Lightspeed, (

There has been a lot of discussion recently regarding the relative merits of Structured ASICs and FPGAs. As an IP company licensing mask-reconfigurable logic arrays, I/Os, and embedded test solutions to semiconductor companies, Lightspeed is in an interesting position to observe the relative merits of each technology. We believe that, in reality, there is a spectrum of logic-implementation technologies and that an economic analysis has to be done for each design to choose the appropriate technology.

Early in our industry’s evolution, semiconductor designs were full-custom–often designed at the transistor level. Both gate-array technology and standard-cell technology emerged in the early 1980s. I started in semiconductor design using 4-micron NMOS and in just a few years had migrated to using leading-edge gate-array technology – 8Kgate CMOS devices. A rough comparison of density and performance put gate-array technology in the neighborhood of 25% that of full-custom design; however, the cost to do a single design was dramatically reduced with gate arrays, as was time to market. Furthermore, re-spin costs were greatly reduced. Standard-cell technology provided improved density and performance, both in the neighborhood of 50% of what was achievable with full-custom implementation, but with increased re-spin time, thus providing another choice. FPGAs gave yet another price/performance option with essentially no re-spin cost. Each of these technology choices involves a variety of tradeoffs to achieve the correct logic implementation solution for a target product:, including engineering time for design and re-spin; masks (full, partial, or none); EDA tool costs; density, yield, and resulting unit cost; and so on.

Moving forward, many SoC-type solutions will have a part of their designs be full-custom (using hard-macros), part standard cell, part mask-reconfigurable, and maybe even a portion that is field-reprogrammable. The architect is challenged to design and partition the system such that these technologies can be maximally utilized. Typical industry figures place FPGA area at 25X that of standard-cell, with a significant power and performance penalty. So, one could not use this technology for the whole design. However, for smaller-gate-count logic that needs to change frequently, embedded FPGAsare very useful. Newer mask-reconfigurable technologies that achieve density close to that of standard cell but with fewer masks to customize allow the use of a “gate array” type of logic for some or all of the synthesizable logic. Several companies offer Platform ASICs, where all of the synthesizable logic is mask-reconfigurable with the RAM, PLLs, and other hard macros being included as before, and perhaps with some of the I/Os also being mask-reconfigurable. A design team can currently create their own Platform ASIC for use within their company – leveraging one base device into multiple derivatives. Other companies are creating CSSPs (Customer Specific Standard Products), where some of the synthesized logic is reconfigurable logic so that each end customer can differentiate their product by having their own specialized IP embedded in the device.

The bottom line is that in today’s capital-intensive development environment, it is necessary to choose the right mix of technologies to achieve overall profitability and time-to-market goals. Having choices is good, as long as the final decision considers the technological and business aspects of all the available silicon technologies and uses the one that best meets the target designs’ performance, price and time-to-market goals.

Comments about this article? Share your thoughts with our readers by contacting the Editorial Director at .

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3. News: 4 Million-Gate Radiation-Tolerant Device for Space Designs

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Actel Corporation unveiled the industry's highest density radiation-tolerant field-programmable gate array (FPGA) for space designs. Their RTAX4000S device expands Actel's antifuse-based RTAX-S family to deliver highly reliable solutions for space applications requiring high gate counts. Sample applications include satellite payload systems, such as data processing applications in communications, and earth observation and scientific satellites. The RTAX4000S devices offer four million system gates (500K ASIC gates) with an I/O count of 840 and 540 Kbits of embedded memory. Because the SEU-hardened RTAX4000S device does not require customer-initiated triple module redundancy, it can deliver more dense effective gate counts than other alternatives. Actel News: Low Profile Socket Simplifies FPGA Prototyping in Space Constrained Applications

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QuickLogic Corporation announced the availability of the HiLo socket from Interconnect Systems, Inc. These development sockets allow designers to easily prototype their space-constrained designs using footprint-compatible sockets. This reduces development costs by allowing the same printed circuit board to be used for prototyping and production. Its 2mm socket height enables low-profile prototypes since the board height, a critical constraint for handheld applications, remains at chip level. To mount, the chip is attached to a pin field and a socket is soldered to the printed-circuit board. The pin field and socket combination accommodates multiple applications including production IC board mounting and board-to-board connections.

QuickLogic Systems > News: Software Development Environment Available for New Processor Families

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Accelerated Technology, a Mentor Graphics division, announced that its Eclipse-powered Nucleus EDGE software development environment is now available for new processor families, including the Nios II family of embedded processors from Altera Corporation, andthe MicroBlaze 32-bit soft processor core and the PowerPC based processors from Xilinx.The Nucleus EDGE software gives field programmable gate array (FPGA) developers an entirely integrated embedded development environment, including an IDE, compiler, debugger and system profiler, with which to create products from concept to deployment. The software also provides developers with full build and debug support for heterogeneous multiprocessor designs, including synchronous control of all of the cores in the system (depending on hardware configuration).

Accelerated Technology > > > News: Tunable Downconverter IP Core Boosts Channel Density for Military Radios and Commercial Wireless

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Pentekis expanding its GateFlow FPGA IP Library to implement a 256-channel narrowband digital downconverter (DDC). Designed for use in Xilinx's Virtex II, Virtex II Pro or Virtex 4 FPGAs, the Model 4954-430 core utilizes a unique architecture to achieve 64 times the channel capacity of conventional quad ASIC downconverters. This intellectual property (IP) core supports applications requiring a high number of digital downconverter channels with size, weight, cost and power constraints, such as military radios and commercial wireless. The architecture uses a channelizer stage that generates 1024 fixed adjacent frequency channels with alias-free performance greater than 75 dB across the passband of each channel.

Pentek, Inc. > International News: Strategic Partnership Targets High-Performance Computing Markets

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Nallatech and Starbridge Systems have formed a strategic partnership that offers software, hardware and services for high-performance computing applications. Their combined offerings make the power of FPGAs accessible to system engineers involved in high-performance computing applications in markets such as defense and military, homeland security and bioinformatics.They provide ease of algorithm development on a wide range of FPGA platforms—from inexpensive low gate-count boards to powerful high-end multi-FPGA architectures. Developers can use the fully integrated, object oriented, graphical development environmentof Starbridge Systems' Viva to create efficient custom circuitry,and then run the complex algorithms directly in the FPGA hardware of Nallatech’s reconfigurable computer systems.

Nallatech Systems > International News: Collaboration to Make Reconfigurable Computing Easier to Programme

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Cray Inc is working with Celoxica Ltd. to make Celoxica’s DK Design Suite available to customers who wish to accelerate their applications using field-programmable gate arrays (FPGAs) integrated into the Cray XD1 supercomputer. The DK Design Suite allows software engineers to implement FPGA-based algorithms using the familiar C language. In reconfigurable computing,users program the FPGAs to act like high-speed, specialized co-processors running special subroutines that speed up parts of the application’s code. As a result, users can solve complex problems in less time without having to increase the size and power budget of their computing platforms.