The Johnson Counter
In some cases, we want a counter that provides individual digit outputs rather than a binary or BCD output. Of course, we can do this by adding a decoder circuit to the binary counter. However, in many cases it is much simpler to use a different counter structure, that will permit much simpler decoding of individual digit outputs.
For example, consider the counting sequence to the right. It actually resembles the behavior of a shift register more than a counter, but that need not be a problem. Indeed, we can easily use a shift register to implement such a counter. In addition, we can notice that each legal count may be defined by the location of the last flip-flop to change states, and which way it changed state. This can be accomplished with a simple two-input AND or NOR gate monitoring the output states of two adjacent flip-flops. In this way, we can use ten simple 2-input gates to provide ten decoded outputs for digits 0-9. This is known as the Johnson counting sequence, and counters that implement this approach are called Johnson Counters.
We could also make an octal counter by using four flip-flops in this configuration. In fact, this is done commercially: the CMOS ICs 4017 and 4022 are counters that implement this technique easily and cheaply. / States / Count
A / B / C / D / E
0 / 0 / 0 / 0 / 0 / 0
1 / 0 / 0 / 0 / 0 / 1
1 / 1 / 0 / 0 / 0 / 2
1 / 1 / 1 / 0 / 0 / 3
1 / 1 / 1 / 1 / 0 / 4
1 / 1 / 1 / 1 / 1 / 5
0 / 1 / 1 / 1 / 1 / 6
0 / 0 / 1 / 1 / 1 / 7
0 / 0 / 0 / 1 / 1 / 8
0 / 0 / 0 / 0 / 1 / 9
/
There is one caveat that must be considered here: The 5-stage circuit uses five flip-flops, and therefore has 32 possible binary states, yet we only use ten states. The 4-stage counter uses only eight of 16 possible states. We must include circuitry that will filter out the illegal states and force this circuit to go towards the correct counting sequence, even if it finds itself in an illegal mode when first powered up. This is not difficult, and the demonstration circuit below includes the necessary gating structure.
The circuit below is logically equivalent to the CMOS 4017 decimal counter, although slightly simplified from the commercial unit.
The demonstration above initially implements only the legitimate counting sequence of the Johnson counter. To allow for all possible illegal combinations and show how they get straightened out, we would need 66 separate images for the overlays, and each image is about 6.5K bytes in size. That's a bit much to ask of many users.
However, you can see the count correction gates operating at the bottom of the counter, and see how they work. The D input to flip-flop C is not directly driven from the B output. Rather, A' and C' are ANDed together, and that combination is NORed with B'. As a result, improper bits reaching flip-flop B get blocked, and flip-flop C can only take on the correct state to reinstate the correct shifting sequence. To see this in action, click on any of the individual flip-flops in the figure. This will force a load of all remaining images and change the state of the selected flip-flop without applying a clock pulse. Then you can watch the behavior of the counter as it removes improper counting sequences. Remember that the download of the additional images may take some time, so please be patient.
You can always identify an illegal counting sequence because more than one output will be high (logic 1). Since each output is enabled by a transition from 0 to 1 or from 1 to 0 in a specific position in the counter, more than one transition will produce more than one output, which is illegal in this context.
Also note that in order to repeatedly invert the shifting bits as they start from flip-flop A, the E' output is fed back to the A flip-flop's D input. This shift does not constitute a second transition here; only when all bits are the same does this appear as a transition.
Of course, these must necessarily be edge-triggered flip-flops clocked simultaneously. The Reset inputs are asynchronous and override the clocking signal. In addition, the CMOS ICs that serve as the model for this demonstration change state on the rising edge of the clock, so this model does the same.
The COUT signal is the Carry Out, which is a symmetrical square wave at one-tenth of the incoming Clock signal frequency. It is quite suitable for clocking a second counter of the same type, to form a multiple-digit decimal counter.