The Analog section of the Front-End Board v. 1.1
(Last updated: November 4, 1999)
S.Argiro’1, D.Camin1,P.Cattaneo2,L.Ratti2,V.Re2,E.Menichetti3,P.Trapani3
1University and INFN, Milano
2University and INFN,Pavia
3University and INFN,Torino
1. Overview of the Front-End Board
We are developing a first version of the Analog section of the Front-End Board (FEB). The Digital section, containing FADC, memories etc, is being developed by the Karlsruhe group [1].The original design and simulation of the channel electronics for the Analog section has been made by the Milano and Pavia groups [2]. The physical implementation, layout and routing of the board has been made by the Torino group, with a lot of work made by S.Argiro’ from Milano. There has been a strong (and lively!) interaction between our Italian groups and the German group in Karlsruhe in all the phases of this design. The plan is to keep this page updated with the modifications and improvements to the design, as well as with the current information on the development of the construction and tests.
2. Design guidelines
Design guidelines for this version 1.1 have been the following:
- Have a full separation of digital and analog worlds (ground, power, signals, controls)
- Implement both the Virtual Channel and Compressor solutions for the dynamic range expansion with respect to the FADC 12 bit capability
- Try to implement all the testing facilities and controls foreseen for a final version, in order to allow for best interconnections with the rest of the trigger and readout system
- Allow for as many programmable controls of the chain as possible, in order to facilitate setting-up and tuning
- Try to minimize as much as possible power consumption
3. Description of the Analog section –version 1.1
The Analog section is a sort of daughter board of the FEB, the mother board being the Digital section. The full FEB is a 9U high, 220 mm deep Eurocard assembly, housed by a standard VME-like crate and power supply. The FEB is made by a 6U high Digital section and a 3U high Analog section, connected vertically by 3 high-density, microminiature 50-pin connectors. The Analog section is also connected to a dedicated analog backplane by one standard 96-pin connector (Fig. 1).
The board contains 22 channels of Front-End analog electronics, serving as many pixels, plus two lower gain virtual channels, meant to add up 11 channels each one. Channels are arranged into two arrays, consisting of eleven elements each one. The first array contains odd numbered channels (1 to 21), the second even ones (2 to 22). Analog differential signals from the Camera Distribution Board are received over the auxiliary (analog) backplane at the top of the read side of the crate, 22 per connector. A list of all the board connections is shown in Appendix A .Signals are then routed through the chain, whose block diagram is shown in Fig. 2 a) and b), for the Virtual Channel and Kompressor options, respectively. Selection between the two options is made by a number of jumpers. It must be stressed that selection between the two operating modes is a mounting option, not a setting one. Therefore, a given board will be equipped with either solution (most likely not changeable), not both. We feel that this feature is still quite useful in order to save money, yet being able to have a careful comparison of the two designs. With the two Virtual channels, the total number of differntial outputs (to the FADC sitting in the Digital section) is 24.
The common signal of each differential input carries a level proportional to the average detector current, with the goal of providing a background signal useful for debugging and control. For this purpose, the common signal is splitted out of the pair and fed to a on-board , Sigma/Delta ADC. The serial output of the ADC is continuously sent to a digital interface in the Digital section.
On the Analog Board a simple circuitry that allows sending pulses to the Head Electronics is implemented. An external pulser is connected to the board either via a pin on the backplane (ATP) or through a Lemo connector located on the front panel. The signal is then routed to two differential line drivers, and sent to the Head Electronics over two twisted-pair cables (TP1OUT+, TP1OUT-,TP2OUT+, TP2OUT). These are meant to be injected at the very front-end, right before the differential line driver from the anode signal to the AB, through a transistor switch. The first twisted pair will serve channels corresponding to 1 through 11 on the AB, while the second will serve channels 12 through 22. In this way, each signal will serve half a column of PMTs on the camera. Two active-low signals, /EN_C1 and /EN_C2, perform the enabling of the drivers on the AB. They are sent out as EN_CxD to the Head Electronics to switch the transistors on. Due to the high occupancy of real estate on both sides of the board, this version won’t contain the special pixel test pulse circuitry developed by the Karlsruhe group. We foresee to add this feature in the next board version, when the issue of compressor vs virtual channel will be solved. In the meantime, injection of pixel test pulses will require a special external box plugging to the rear connector.
Chain control and setting is performed with some flexibility, upon changing the value of one or two programmable potentiometers. For the Virtual Channel option, a single programmable pot per channel will fix the gain of the input stage. For the Compressor option, a pair of programmable pots will fix the (common) breakpoints of the two arrays of odd and even channels. Individual programmable pots will fix the gain of the output stage of each channel.
Power levels have been kept as low as possible, nevertheless it must be clearly stated that power minimization was not our first task in this version of the board. With the present levels of power supply voltage, we anticipate a linear range of 0-+4 V for our output signals, well matched by the available FADC input range
4. Status of the project (09/09/1999)
Several changes have been made to the original design during last July and the second half of August, some as a consequence of comments, remarks and requests by our colleagues in Karlsruhe. We believe most of these changes are real improvements, well worth the extra effort and time they have required. We have now just completed the editing of the full schematics and layout of the board. Routing has been started, and we plan to order the first 8 PCB (176 input channels) shortly. Orders for the components are being sent. We do not anticipate time-critical parts. We hope to have a few boards mounted by end of October
Update (4/11/1999)
Three Analog Boards will be built shortly; two of them will be equipped in the VC mode and one in the Kompressor mode. Procurement of the various parts is underway, routing almost completed. The goal is to have these boards tested by the end of november.
Appendix A
SIGNAL DESCRIPTION:
POWER LINES:
INPUT
/Where
/Dig/An
/I
A
/Turns
into
/I
mA
/Meaning
+V(9V) / A27,B27,C27
On P0 / A / <1.0
(VC) / +Va1 / <800 / Regulated to +5V
Serves Analog Channels 1-3-5-7
<1.5
(K) / +Va2 / <800 / Serves Analog Channels 9-11-13-15
+Va3 / <800 / Serves Analog Channels 17-19-21-23
+Va4 / <800 / Serves Analog Channels 2-4-6-8
+Va5 / <800 / Serves Analog Channels 10-12-14-16
+Va6 / <800 / Serves Analog Channels 18-20-22-24
-V
(-9V) / A28,B28,C28
On P0 / A / <1.0
(VC) / -Va1 / <800 / As above for negative polarity
<1.5
(K) / -Va2 / <800
-Va3 / <800
-Va4 / <800
-Va5 / <800
-Va6 / <800
±V
(±9V) / As above / A / ±VM / <100 / Regulated to ±5V powers the two
Differential line drivers on
sheet TPULSE
+V / As above / A / +V_SD / <100 / Regulated to +5V,powers the analog
Sections of the four AD73360 on
sheet ADCs
+5V or +3.3V / JDH1 A18,B18, A17,B17 / D / VDD / <200 / Powers the Digital section of the
AD73360 Jumper JP178 on sheet
CONNECTORS connects to +3.3V or
+5V(default)
+5V / JDH1
A18,B18 / D / +5V,VCC / <200 / Powers the few digital interfaces
of the HCT or ACT series, for
TTL/CMOS compatibility
+5V_A / P0 A29, B29,C29 / A / +5V_A
on JDH1,
JDH2,
JDH3 / ? / Serves the FADCs on the Digital
Board
-12V / C30 on P0 / A / <100 / Used to enable the NPN transistor
on the HE to allow injection of
TP
DIGITAL CONTROLS
DPOT
DCS[0..3] / JDH2 A7,A8,B7,B8 / 4 in 16 decoding for Chip select of the 7 DPOTAfter decoding CS[0..6] on page DPOT Note that when no chip is selected a Null code must be
set (e.g. 1111)
PSDI, PSDO / JDH2 A9,B9 / Serial I/O for the DPOT. The chips are connected in parallel
MCLK / JDH3 A19 / MCLK (10Mhz)is sent to the DPOTS as CLK only when a chip is selected
GI[1..24] / Sheets DPOT, Channels / Connected to the terminals of the potentiometers, Gain controls
GO[1..24] / As Above
BPA,BPB / Kompressor Break-Point control
VBIAS[1..2] / DPOT, ADCs / allows biasing the reference to the AD73360
ADCs (AD73360)
SDIFS, SDOFS / A22,B22 / Frame sync signals for operation of the Ad73360 Serial PortSDI, SDO / JDH3 A21,b21 / Serial Data I/O
SE / JDH3 A20 / Serial Port Enable
RESET / JDH3 B20 / Reset
MCLK / JDH3 A19 / Master Clock (10Mhz)
SCLK / JDH3 B19 / Serial Port clock (out from ad73360, made from MCLK divided by some programmable ratio)
GREF1,GREF2 / JDH3 A12, A25 on P0 / Ground reference (shield) for inputs 1-11 and 12-22
VBIAS[1..2] / see DPOT
TPULSE
TP_IN / Front panel orATP (A30 on P0) / Test Pulse In
/EN_C1, /EN_C2 / JDH2 B6, JDH3 B15 / Active low, enables test pulsing on channels 1-11 or 12-22
EN_C1D, EN_C2D / P0 C12, C25 / 0 or -12V to enable test pulsing on the Head
TP1OUT+, TP1OUT-
TP2OUT+, TP2OUT- / A13, A26, C13, C26 on P0 / Test Pulse Out to HE
on two twisted-pairs
ANALOG Channels
+V[1..22] / P0 A1-A11, C1-C11 / Differential input-V[1..22] / P0 A14-A24, C14-C24
VOUT[1..22] / JDH 1,2,3 / output signal
SGND[1..24] / output signal ground reference
VOUT23 / JDH 2 / virtual channel :
sum of odd channels
VOUT24 / JDH 3 / virtual channel: sum of even channels
Figure 1 : Board Layout
Connector J1 / Connector J2 / Connector J3Pin #
/row a
/row b
/row a
/row b
/row a
/row b
1 / SGnd01 / Vout01 / SGnd21 / Vout21 / Vout14 / SGnd142 / AGND / AGND / AGND / AGND / AGND / AGND
3 / Vout03 / SGnd03 / Vout23 / SGnd23 / SGnd16 / Vout16
4 / +5V_A / AGND / AGND / AGND / +5V_A / AGND
5 / SGnd05 / Vout05 / Spare_1 / Spare_2 / Vout18 / SGnd18
6 / AGND / AGND / Tp21(nc) / En_C1 / AGND / AGND
7 / Vout07 / SGnd07 / DCS2 / DCS3 / SGnd20 / Vout20
8 / +5V_A / AGND / DCS0 / DCS1 / +5V_A / AGND
9 / SGnd09 / Vout09 / PSDI / PSDO / Vout22 / SGnd22
10 / AGND / AGND / VDD / DGND / AGND / AGND
11 / Vout11 / SGnd11 / Tp02(nc) / Tp04(nc) / SGnd24 / Vout24
12 / +5V_A / AGND / Tp06(nc) / Tp08(nc) / AGND / AGND
13 / SGnd13 / Vout13 / Tp10(nc) / Tp12(nc) / Tp14(nc) / Tp16(nc)
14 / AGND / AGND / AGND / AGND / Tp18(nc) / Tp20(nc)
15 / Vout15 / SGnd15 / Vout02 / SGnd02 / Tp22(nc) / En_C2
16 / +5V_A / AGND / +5V_A / AGND / DGND / DGND
17 / SGnd17 / Vout17 / SGnd04 / Vout04 / VDD / VDD
18 / AGND / AGND / AGND / AGND / +5Vdig / +5Vdig
19 / Vout19 / SGnd19 / Vout06 / SGnd06 / MCLK / SCLK
20 / +5V_A / AGND / +5V_A / AGND / SE / RESET
21 / Tp01(nc) / Tp03(nc) / SGnd08 / Vout08 / SDI / SDO
22 / Tp05(nc) / Tp07(nc) / AGND / AGND / SDIFS. / SDOFS
23 / Tp09(nc) / Tp11(nc) / Vout10 / SGnd10 / Pos0 / Pos1
24 / Tp13(nc) / Tp15(nc) / +5V_A / AGND / Pos2 / Pos3
25 / Tp17(nc) / Tp19(nc) / SGnd12 / Vout12 / Pos4 / PosRef
Spare_1 and Spare_2 are connected to the FPGA (function to be defined later)
Connector P0
1 / V+1 / AGnd / V-1 / Differential Input of PMT#1, 4Vpp ± 2.5 V relative to GRef1
2 / V+2 / AGnd / V-2
3 / V+3 / AGnd / V-3
4 / V+4 / AGnd / V-4
5 / V+5 / AGnd / V-5
6 / V+6 / AGnd / V-6
7 / V+7 / AGnd / V-7
8 / V+8 / AGnd / V-8
9 / V+9 / AGnd / V-9
10 / V+10 / AGnd / V-10
11 / V+11 / AGnd / V-11
12 / GRef1 / AGnd / EN_C1D / Reference for CM chn 1..11 and testpulse enable
13 / TPO1+ / AGnd / TPO1- / Differential test pulse for chn 1..11 to HE
14 / V+12 / AGnd / V-12
15 / V+13 / AGnd / V-13
16 / V+14 / AGnd / V-14
17 / V+15 / AGnd / V-15
18 / V+16 / AGnd / V-16
19 / V+17 / AGnd / V-17
20 / V+18 / AGnd / V-18
21 / V+19 / AGnd / V-19
22 / V+20 / AGnd / V-20
23 / V+21 / AGnd / V-21
24 / V+22 / AGnd / V-22
25 / GRef2 / AGnd / EN_C2D / Reference for CM chn 12..22 and testpulse enable
26 / TP2O+ / AGnd / TP2O- / Differential testpulse for chn 12.22 at HE
27 / +V1 / +V2 / +V3 / +V[1..3]: positive analog supply voltage (to be defined +5..+12 V ). Total current per slot: < 1500 mA (kompressor mode) , <1000 mA (VC mode)
28 / -V1 / -V2 / -V3 / -V[1..3]: negative analog supply voltage (to be defined -5..-12 V ). Total current per slot: < 1500 mA (kompressor mode) , <1000 mA (VC mode)
29 / +5V_A / +5V_A / +5V_A / analog +5V for FADCs ; total current per slot: < 1000 mA
30 / ATP / Spare / -12V / ATP: Analog Amplitude of testpattern generator (from 2.LTB) range: to be defined
-12 V for TP enabling
31 / Pos0 / Pos1 / Pos2 / Pos[0..3]base address of slot position
32 / Pos3 / PosRef / Pos4 / PosRef: reference for Pos[0..3], logical 1 = pull down to PosRef
Spare: spare line, may be defined later