SYSTEM SOFTWARE ( CS 2304) UNIT - I

INTRODUCTION

What is system software?

System software consists of a variety of programs that support the operation of a computer.

System programs were developed to make computers better adapted to the needs of their users.

It allows us to focus on application without knowing details of machine.

Examples of system software are text editor, compiler, loader or linker, debugger, macro processor, operating system etc.

  • Text editor is used to create and modify the program.
  • Compiler translate the user program into machine

language

  • Loaders are system programs that prepare machine

language programs for execution

  • Debugger helps to detect errors in the program.
  • A translator is used to translate the assembly code into

machine code. This translator is called an assembler.

The most important system software is the OS, which is an integrated system of programs that manages the system resources, and provides various support services such as the computer executing the application programs of users

SYSTEM SOFTWARE AND MACHINE ARCHITECTURE

System software is different from application software as follows.

APPLICATION SOFTWARE / SYSTEMSOFTWARE
  1. It concerns with solution of some problem.
  1. Its focus is on the application not on the computing system.
/ It supports the operation and use of the computer.
It is related to the architecture of the machine on which they are to run.
(i.e.) Most of the system software is machine dependent.

Machine dependency

We discuss how the system software dependent on machine architecture.

Assembler – Assembler translates mnemonics instructions into machine code. These mnemonics instructions involves different types of instruction sets, instruction formats, addressing modes, etc. that varies from one machine architecture to another. Hence the assembler design depends on machine architecture.

Complier – It translates high level language code into machine code. It involves the following 5-phases,

  1. Lexical phase
  2. syntactic analysis phase
  3. Intermediate code generation phase
  4. code optimization phase
  5. code generation phase

Machine independency

There are some aspects of system software that do not directly depend upon the type of computing system being supported.

  • Assembler – The general design and logic of an assembler is basically the same on most computers.
  • Compilers – The first three phases of compiler discussed in the previous section are independent of the machine architecture.

Some of the code optimization techniques like common sub expression elimination, dead code elimination, etc. are also independent of the target machine.

  • Linker – Linker combines the independently assembled sub programs into a single module.

The sub programs are independently assembled into object modules. These object modules are linked by the linker. The process of linking is machine independent

THE SIMPLIFIED INSTRUCTIONAL COMPUTER (SIC)

We describe the architecture of Simplified Instructional Computer (SIC) in terms of memory, registers, instruction format, data format, addressing modes, instruction set, input and output. This machine has been designed to illustrate the most commonly encountered hardware features and concepts that are often found in real machines.

Versions of SIC

SIC comes in two versions.

  1. The standard model.
  2. an XE version (XE stands for “extra equipment” or “extra expensively)

These two versions have been designed to be “upward compatible”, means that an object program for the standard SIC machine will also execute properly on a SIC / XE system. Such upward compatibility is often found on real computers that are closely related to one another.

SIC Machine Architecture

SIC / XE Machine Architecture

SIC Programming Examples

SIC Machine Architecture

Memory

  • Memory consists of 8-bit bytes
  • 3 consecutive bytes form a word (24 bits)
  • All addresses of SIC are byte addresses
  • Words are addressed by the location of their lowest numbered byte.
  • There are total of 32,768 (2^15) bytes in the computer memory

Registers

  • There are five registers each is 24 bits in length.
  • The following table indicates the numbers, mnemonics and uses of these registers

Mnemonics / Number / Special Use
A / 0 / Accumulator, used for arithmetic operation
X / 1 / Index register, used for addressing
L / 2 / Linkage register, the Jump to Subroutine (JSUB) instruction stores the return address in this register.
PC / 8 / Program Counter, contains the address of the next instruction to be fetched for execution.
SW / 9 / Status word, contains a variety of information, including a condition code (CC)

The numbering scheme has been chosen for compatibility with the XE version of SIC. i.e., number 3 to 7 is used by SIC / XE.

Data formats

  • Integers are stored as 24-bit binary number
  • Negative values are represented as 2’s compliment representation.
  • Characters are stored using their 8-bit ASCII codes
  • There is no floating point hardware on the standard version of SIC.

Instruction formats

  • All machine instructions on the standard version of SIC have

the 24-bit format as follows:

8 1 15

Opcode / X / Address
  • The flag bit x is used to indicate indexed addressing mode.

Addressing modes

There are two addressing modes available, by setting the x bit of the instruction. They are:

Mode / Indication / Target Address Calculation
1. Direct / X=0 / TA = address
2. Indexed / X=1 / TA = address + (X)
(Parenthesis are used to indicate the contents of a register or memory location)

(X) – Content of Index register

Instruction Set

SIC provides a basic set of instructions that are sufficient for most simple tasks. It includes:

Load and Store instructions

LDA, LDX, STA, STX, etc.

Arithmetic instructions

ADD, SUB, MUL, DIV

(Ex) ADD WORD (Adds register A with memory WORD and result is stored in A)

Comparison instruction

COMP

(ex) COMP WORD (Compares the value in register A with WORD and sets condition code CC to indicate the result <, = or >)

Condition jump instruction

JLT, JEQ, JGT

These instructions can test the setting of CC and jump accordingly.

Subroutine linkage instruction

JSUB – jumps to the subroutine, placing the return address in register L.

RSUB – returns by jumping to the address contained in register L.

Input and output

  • Input and output is performed by transferring 1 byte at a time or from the rightmost of bits of register A.
  • Each device is assigned a unique 8-bit code.
  • There are three input / output instructions with device code as operand namely TD, RD and WD.
  • TD – Test Device instruction sets whether the addressed device is ready to send or receive a byte of data. CC is set for the result.
  • A setting of < means that the device is ready to send or receive
  • A setting = means that the device is not ready.
  • A program needing to transfer data must wait until the device is ready then execute

Read Data (RD) or Write Data (WD)

  • This sequence should be continual for each byte of delta.

SIC / XE MACHINE ARCHITECTURE

  • Memory
  • Registers
  • Data formats
  • Instruction formats
  • Addressing modes
  • Input and output

Memory

The memory structure for SIC / XE is the same as SIC standard model memory. The maximum memory on SIC / XE is1 MB (2^20 bytes). This increase leads to change in instruction formats and addressing modes.

Registers

Mnemonics / Number / Special Use
A / 0 / Accumulator, used for arithmetic operation
X / 1 / Index register, used for addressing
L / 2 / Linkage register, the Jump to Subroutine (JSUB) instruction stores the return address in this register.
B / 3 / Base register, used for addressing
S / 4 / General working register – no special use
T / 5 / General working register no special use
F / 6 / Floating point accumulator (48 bits)
PC / 8 / Program Counter, contains the address of the next instruction to be fetched for execution.
SW / 9 / Status word, contains a variety of information, including a condition code (CC)

Data formats

1 11 36

S / Exponent / fraction

Instruction formats

Format (1 byte)

Format ( 2 bytes)

Format (3 bytes)

Format ( 4 bytes)

Format 1 (1 byte):

op {8}

Format 2 (2 bytes):

op {8} / r1 {4} / r2 {4}

Format 3 (3 bytes):

op {6} / n / i / x / b / p / e / displacement {12}

Format 4 (4 bytes):

op {6} / n / i / x / b / p / e / address {20}

Formats 3 & 4 introduce addressing mode flag bits:

  • n=0 & i=1

Immediate addressing - TA is used as an operand value (no memory reference)

  • n=1 & i=0

Indirect addressing - word at TA (in memory) is fetched & used as an address to fetch the operand from

  • n=0 & i=0

Simple addressing TA is the location of the operand

  • n=1 & i=1

Simple addressing same as n=0 & i=0

Flag x:

x=1 Indexed addressing add contents of X register to TA calculation

Flag b & p (Format 3 only):

  • b=0 & p=0

Direct addressing displacement/address field containsTA (Format 4 always uses direct addressing)

  • b=0 & p=1

PC relative addressing - TA=(PC)+disp (-2048<=disp<=2047)*

  • b=1 & p=0

Base relative addressing - TA=(B)+disp (0<=disp<=4095)**

* note - in PC relative, disp is interpreted as a 12 bit signed integer in 2's complement

** note - in Base relative, disp is interpreted as a 12 bit unsigned integer

Flag e:

e=0 use Format 3

e=1 use Format 4

Input and Output (I/O):

  • 28 (256) I/O devices may be attached, each has its own unique 8-bit address
  • 1 byte of data will be transferred to/from the rightmost 8 bits of register A

Three I/O instructions are provided:

  • RD Read Data from I/O device into A
  • WD Write data to I/O device from A
  • TD Test Device determines if addressed I/O device is ready to send/receive a byte of data. The CC (Condition Code) gets set with results from this test:

device is ready to send/receive

= device isn't ready

SIC/XE Has capability for programmed I/O (I/O device may input/output data while CPU does other work) - 3 additional instructions are provided:

  • SIO Start I/O
  • HIO Halt I/O
  • TIO Test I/O .

Example Programs

Simple data and character movement operation

LDAFIVE

STAALPHA

LDCHCHARZ

STCHC1

.

ALPHA RESW1

FIVE WORD5

CHARZ BYTE C’Z’

C1 RESB1

Arithmetic operationsProgram

LDA ALPHA

ADD INCR

SUB ONE

STA BEETA

……..

……..

……..

……..

ONE WORD 1

ALPHA RESW 1

BEETA RESW 1

INCR RESW 1

Looping and Indexing operation Program

LDX ZERO : X = 0

MOVECH LDCH STR1, X : LOAD A FROM STR1

STCH STR2, X : STORE A TO STR2

TIX ELEVEN : ADD 1 TO X, TEST

JLT MOVECH

.

.

.

STR1 BYTE C ‘HELLO WORLD’

STR2 RESB 11

ZERO WORD 0

ELEVEN WORD 11

Input and Output operation Program

INLOOP TD INDEV : TEST INPUT DEVICE

JEQ INLOOP : LOOP UNTIL DEVICE IS READY

RD INDEV : READ ONE BYTE INTO A

STCH DATA : STORE A TO DATA

.

.

OUTLP TD OUTDEV : TEST OUTPUT DEVICE

JEQ OUTLP : LOOP UNTIL DEVICE IS READY

LDCH DATA : LOAD DATA INTO A

WD OUTDEV : WRITE A TO OUTPUT DEVICE

.

.

INDEV BYTE X ‘F5’ : INPUT DEVICE NUMBER

OUTDEV BYTE X ‘08’ : OUTPUT DEVICE NUMBER

DATA RESB 1 : ONE-BYTE VARIABLE

To transfer two hundred bytes of data from input device to memory

LDX ZERO

CLOOP TD INDEV

JEQ CLOOP

RD INDEV

STCH RECORD, X

TIX B200

JLT CLOOP

.

.

INDEV BYTE X ‘F5’

RECORD RESB 200

ZERO WORD 0

B200 WORD 200

Subroutine to transfer two hundred bytes of data from input device to memory

JSUB READ

………….

………….

READ LDX ZERO

CLOOP TD INDEV

JEQ CLOOP

RD INDEV

STCH RECORD, X

TIX B200 : add 1 to index compare 200 (B200)

JLT CLOOP

RSUB

……..

……..

INDEV BYTE X ‘F5’

RECORD RESB 200

ZERO WORD 0

B200 WORD 200

Example Programs (SIC/XE)

Simple data and character movement operation

LDA#5

STAALPHA

LDA #90

STCHC1 .

.

ALPHA RESW1

C1 RESB1

Arithmetic operations

LDS INCR

LDA ALPHA

ADD S,A

SUB #1

STA BETA

………….

…………..

ALPHA RESW 1

BEETA RESW 1

INCR RESW 1

Looping and Indexing operation

LDT #11

LDX #0 : X = 0

MOVECH LDCH STR1, X : LOAD A FROM STR1

STCH STR2, X : STORE A TO STR2

TIXR T : ADD 1 TO X, TEST (T)

JLT MOVECH

……….

……….

………

STR1 BYTE C ‘HELLO WORLD’

STR2 RESB 11

To transfer two hundred bytes of data from input device to memory

LDT #200

LDX #0

CLOOP TD INDEV

JEQ CLOOP

RD INDEV

STCH RECORD, X

TIXR T

JLT CLOOP

.

.

INDEV BYTE X ‘F5’

RECORD RESB 200

Subroutine to transfer two hundred bytes of data from input device to memory

JSUB READ

……….

……….

READ LDT #200

LDX #0

CLOOP TD INDEV

JEQ CLOOP

RD INDEV

STCH RECORD, X

TIXR T : add 1 to index compare T

JLT CLOOP

RSUB

……..

……..

INDEV BYTE X ‘F5’

RECORD RESB 200

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