Supplement to III-V Roadmap Report

Case Study – Si Compatible GaN Power Electronics

Background:GaN power electronics was the first of the topics identified in the III-V Roadmap exercise (identified in the report as ‘efficient power electronics’) to receive major funding in the form of an EPSRC Programme Grant. It was felt that it would be helpful to relay to the community the process leading up to the funding.

Timeline

  1. Although not one of the top scorers in the matrix table produced in the Roadmap report, ‘efficient power electronics’ came out strongly in the Roadmap meetings in early 2011. The topic was picked out again when ‘GaN Power Electronics’ was identified in a list of three important themes from the independent National Centre for III-V Technologies Strategy Committee to be recommended for prioritisation for future work-up into collaborative programmes.
  2. An informal working group of interested partiesemerged and a leader was identified at an early stage in order to bring focus and direction to the working group. The first meeting of the working group took place in August 2011 in Glasgow, followed in the autumn by a meeting in Cambridge then one in Nottingham early in 2012. It was during these meetings that the scope of the proposed work, together with the partners, was identified.It was very important at that stage to identify the partners required to give complete coverage of the expertise required to address the proposed objectives but, equally important, without an overlapin capability.
  3. The BIS report, “POWER ELECTRONICS: A STRATEGY FOR SUCCESS” published in October 2011 was very timely and this was followed by a call in February 2012 to establish the multi-site virtual Centre of Excellence in Power Electronics which was EPSRC’s response to the BIS report.Although EPSRC’s call was independent of the ‘GaN Power Electronics’ plans, considerable momentum was gained by the proposal at this stage.
  4. The key technical challenges and constraints were identified and provisional solutions devised. The main ones were:
  • GaN on Si for cost
  • Si process compatibility
  • Normally-off HFETs
  • Vertical structures to compete on performance
  1. Links with industry were formed and strengthened using the technical challenges as points of discussion.
  2. Proposal writing then took place with detailed definition of work packages and assigned responsibilities. Residual ‘political’ problems were then ironed out.

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