0606FR-Wireless.doc
Keywords: analog, RF, wireless, IP, models, integration
@head: Analog-RF IP Integration Challenges SoC Designers
@deck: As market forces continue to push more analog and RF functionality into digital SoCs, designers face a host of development issues.
@text: The global consumer market for ever-smaller, ever-more feature-rich wireless products continues to grow. At the same time, the challenges facing analog and RF designers of SoC platforms also are increasing. Design challenges and solutions therefore abound. Most of these solutions center around the reuse of existing wireless-RF designs--either in-house or from commercial analog IP vendors. Although IP solves some problems, however, it invites others. Let’s consider the challenges facing analog designers/testers and then look at some innovative solutions.
Analog-RF Challenges Abound
Before specific analog and RF problems can be addressed, we must differentiate between two types of chip implementation: pure analog and analog system-on-a-chip (SoC). The analog and RF IP that are designed to be integrated into SoCs can be different from those targeted exclusively for analog-RF chips, notes Anthony Gadient, Virtuoso Marketing Group Director at Cadence ( The digital portion of an SoC, being discrete in nature, generates an abundance of noise. That noise must be taken into account when integrating the analog-RF portion.
As Gadient explains, isolation techniques can be used to shield the analog and RF portion of an SoC from noisy digital neighbors. But isolation alone is rarely sufficient to resolve all noise issues. Other techniques must be tried to increase the noise immunity of the analog and RF IP, such as differential design, clever frequency allocation, use of clean power-supply pads, etc. The digital part of the SoC also can be designed to accommodate sensitive neighbors through the use of clock dithering.
If analog and RF IP could be delivered with a guaranteed level of isolation from its surroundings, integration with the digital portion of an SoC would be simplified, notes Dr. Jim Lansford, CTO of Alereon Inc. “Unfortunately, the mixed-signal IP handoff is clumsy and requires significant designer intervention.” One solution, observes Dr. Lansford, might be a set of standard interface rules (at the layout level) that could be defined so that the IP owner can guarantee a certain amount of design isolation if the IP receiver follows a set of stated rules.
But providing such interface rules requires that analog and RF IP must come in well-understood models just like most digital IP. This isn’t usually the case, says Dr. Lansford. Instead, mixed-signal IP often appears as a GDSII netlist and an extracted netlist. These models aren’t sufficient to let a designer know whether or not a design is being integrated correctly. The complex rules governing the relationships between RF blocks again require SPICE netlists to be ripped open and simulated, according to Dr. Johnson. [For a more detailed discussion of SPICE simulation/modeling techniques, see “Analog Issues Confront Digital Designers,” Chip Design, April/May 2005.]
In regards to IP standards, two prominent trade organizations have been working to develop some standards for analog IP integration. The Spirit Consortium, which includes major EDA vendors and European SoC developers, is attempting to make IP reusable with minimal effort from engineers. Similarly, the VSI-Alliance is developing the technical standards that are required to enable the mixing and matching of analog IP cores from multiple sources.
Modeling and Simulation
The most often-touted benefits of incorporation-proven analog and RF IP are improved time to market and lower cost. But what does “proven” really mean in the analog world? This question is posed by Jon Strange, Director of RF Engineering in the RF and Wireless Systems division of Analog Devices Inc. ( Strange answers that the term “proven” can encompass anything from “the simulations looked OK” to comprehensive test data in a real or emulated network environment. If integrated with other functions/IP (for example, large digital blocks), the subsequent impact on performance will resonate with those that have played “hunt the spur” on any complex mixed-signal/RF IC.
The quick and accurate modeling and simulation of analog and RF behavior has always been a problem. Just consider the modeling and simulation of parasitics. Most designers use a parasitic-extraction utility at layout to verify the circuit performance with the modeled silicon. But such implementation details, such as layout parasitics, must be modeled approximately in order to make the system-level simulation run quickly, states Colin Warwick, RF Product Manager at The MathWorks Inc. ( This need for speed is a result of the subtle complexity of analog and RF circuits. As Warwick explains, “The merger of RF and system [SoC] is confounded by the conflicting need for small time steps (i.e., roughly the size of the carrier period) to avoid aliasing the carrier and its harmonics and large time steps (i.e., roughly the size of the symbol period) in order to calculate bit error rate (BER) in a reasonable time.”
Parasitics, on-chip passives (like spiral inductors), and substrate crosstalk are just some of the challenges facing the IC integration of the analog and digital domains. This statement is especially true for multi-band and multi-standard wireless transceivers, observes Dr. Sotiris Bantas, VP, Technology, Helic S.A. “For instance, an Ultra-Wide Band (UWB) low-noise amplifier (LNA) typically employs 6 to 8 integrated inductors. Magnetic coupling between them and other inductors on chip (e.g., multiple VCO tanks) can seriously affect system performance or even lead to design failure. Similar arguments apply for substrate coupling--especially on CMOS substrates.”
These issues affect the integration of multiple RF cores on the same die. Modeling and optimization tools attempt to address these modern transceiver challenges by providing increased automation, early estimation of RF parasitics (as opposed to final-layout signoff extraction), and tool-assisted floorplanning, notes Dr. Bantas.
But parasitic problems extend beyond the chip level to exacerbated designers at the package level. While package design was traditionally outside the realm of chip development, such issues are now becoming a system-level concern. The experts at AMI Semiconductor explain that a lack of detailed understanding of the electrical parasitics arising from the packaged product is becoming a key problem for chip designers.
Chip and package co-design and analysis tool packages are beginning to gain momentum in the EDA community. Just look at the recent package-aware, chip-design software startup called Rio Design Automation ( Or consider a mature analog and RF company like Applied Wave Research ( Tom Quan, VP of Marketing at AWR, explains that analog and digital design-integration issues can be addressed with a unified chip/package/module co-design methodology. Quan notes that such an approach should be capable of analyzing high-frequency signals spanning multiple technology domains (i.e., time and frequency domain as well as from within the chip, through the package, and onto the module/PCB substrate).
Process Variations
At 90-nm and below geometries, designers of SoCs with analog and RF IP face a new set of issues. Foremost among these challenges is the process variation in the manufacturing of silicon. The core has to be verified across the spectrum for this variability. Typically, not all cases can be covered due to slow simulation speed, schedule pressures, and lack of automation, explains Sandipan Bhanot, CEO of Knowlent Corp. (
To compensate for this lack of coverage, designers will typically add a lot of programmability to the core. Examples include settings like voltage swing control, pre-emphasis ratio settings, clock frequency adjustments, etc. “But adding this programmability makes the verification challenge explode,” Bhanot observes. Now the designers need to check each and every mode for each and every programmability setting across the corners. This task is almost physically impossible to do at the Spice level. Designers therefore need to start thinking about mixed-signal methodologies.
One way to address wafer-level process issues is with fast and accurate RF model parameter extraction, observes Larry Dangremond, Segment Marketing Manager for Cascade Microtech ( He notes that high-accuracy, on-wafer model parameter extraction affects the number of design turns, time to market, and profitability.
In addition to modeling, simulation, and process-variation improvements, verification remains one of the best ways to ensure good integration of the analog and RF IP. But verification remains a tricky task, notes Tom Ferry, VP of Marketing for Berkeley Design Automation Inc. ( The biggest problem is that the EDA tools are not fast enough to deal with large circuits. In addition, Ferry points out that the accuracy at 90 nm and below is very demanding.
As tricky as proper verification can be for in-house analog and RF design teams, it’s even more difficult for IP vendors. They must create analog and RF IP that must work in a digital CMOS process. But the vendors don’t know where the IP will be located on the customer's SoC. Navraj Nandra, Director of Mixed-Signal IP for Synopsys Solutions Group ( offers just one of the challenges: “For example, 65-nm technologies require reduced supply voltages to avoid hot carrier effects. Although this does not have an impact on the design of the digital IP, the reduced supply voltage or dynamic range has a significant impact on the design of the analog IP.” One solution that the IP vendor can implement is to create analog blocks that give sufficient dynamic range by using I/O devices and good layout techniques. This approach will avoid the issues caused by common submicron-process problems.
This report offers insights into the challenges and solutions that arise when integrating analog and RF IP into SoC designs. The Table includes all of the companies listed in this report along with many of the key players in the analog market. All of them will help today’s SoC designer create the best products possible in the shortest amount of time. The final solution to the analog-digital integration problem remains elusive, however. It will continue to challenge the next generation of chip designers.