Deliverable D7.7 Page 1 of 13
REALITY
Reliable and Variability tolerant System-on-a-chip Design in More-Moore Technologies
Contract No 216537
Deliverable D7.9
Final project report
Editor: / Miguel MirandaCo-author / Acknowledgement: / The REALITY Consortium
Status - Version: / V1.0
Date: / 28/10/2010
Confidentiality Level: / Public
ID number: / IST-216537-WP7-D7.9
© Copyright by the REALITY Consortium
The REALITY Consortium consists of:
Interuniversity Microelectronics Centre (IMEC vzw) / Prime Contractor / BelgiumSTMicroelectronics S.R.L. (STM) / Contractor / Italy
Universita Di Bologna (UNIBO) / Contractor / Italy
Katholieke Universiteit Leuven (KUL) / Contractor / Belgium
ARM Limited (ARM) / Contractor / United Kingdom
University Of Glasgow(UoG) / Contractor / United Kingdom
IST-216537-WP7-D7.7-v1.0.doc© REALITY Consortium
Deliverable D7.4Page 1 of 20
1.Disclaimer
The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability.
2.Acknowledgements
The REALITY consortium acknowledges the contributions from the former project coordinators: Peter Lemmens and Tom Tassignon, who were members of the former Project Office Support group of the Nomadic Embedded Systems (NES) division of imec (today discontinued). Such group had no technical focus and it t was fully devoted to support the different NES’s R&D units in the administrative, legal and non-technical reporting tasks of the projects under their management.
Today, both coordinators remain affiliated to imec,. Peter Lemmens was the first REALITY project coordinator for about one year, between January 2008 and September 2008. Peter is still active at the imec office in Taiwan. Tom was with REALITY for about half year, between October 2008 and April 2009 and he is at the time of writing this report on sabbatical leave.
On May 2009, the project coordination activities were transferred to Miguel Miranda who has been the technical leader of the project throughout the whole duration. Miguel was the last project coordinator of REALITY for about 15 months, until its finalization date.
3.Document revision history
Date / Version / Editor/Contributor /Comments
28/10/2010 / V1.0 / Miguel Miranda / First & final draft4.Preface
The scopeand objectives of the REALITY project are:
- Development of design techniques, methodologies and methods for real-time guaranteed, energy-efficient, robust and adaptive SoCs, including both digital and analogue macro-blocks“
The Technical Challenges are :
- To deal with increased static variability and static fault rates of devices and interconnects.
- To overcome increased time-dependent dynamic variability and dynamic fault rates.
- To build reliable systems out of unreliable technology while maintaining design productivity.
- To deploy design techniques that allow technology scalable energy efficient SoC systems while guaranteeing real-time performance constraints.
Focus Areas of this project are :
- “Analysis techniques” for exploring the design space, and analysis of the system in terms of performance, power and reliability of manufactured instances across a wide spectrum of operating conditions.
- “Solution techniques” which are design time and/or runtime techniques to mitigate impact of reliability issues of integrated circuits, at component, circuit, architecture and system (application software) design.
The REALITY project has started its activities in January 2008 and is planned to becompleted after 30 months. It is led by Dr. Miguel Miranda of IMEC. The Project Coordinatoris Dr. Miguel Miranda from IMEC. Five contractors (STM, ARM, KUL, UoG, UNIBO)participate in the project. The total budget is 2.899 k€.
5.Abstract
This report isdeliverable D7.9: “Final report”. It provides an executive summary of the project after its 2.5 years lifespan. It summarizes the awareness created by the project outcome and its implications in society. In addition, and to attend the requests expressed by the expert reviewers during the final review meeting, the project also summarizes the main valorisation actions among the different the consortium partners.
6.Table of contents
1.Disclaimer
2.Acknowledgements
3.Document revision history
4.Preface
5.Abstract
6.Table of contents
7.Executive Summary
8.Summary description of the project context and objectives
9.Description of the main scientific & technical results achieved
10.Potential Impact
11.Main dissemination activities and exploitation of results
12.Plan for use and dissemination of foreground
12.1.Use by industrial partners in proprietary products
12.1.1.STMicroelectronics.
Hybrid design flow for Statistical Static Timing Analysis
REALITY: not only technical achievements
12.1.2.ARM Ltd.
Variability Characterization:
Importance of variability aware design
Beyond the technical discussions
12.1.3.Gold Standard Simulations Ltd.
13.Project management
13.1.Impact of deviations materialized from the planned milestones and deliverables along the project execution
13.2.Development of the Project website :
13.3.Use of foreground and dissemination activities along the project:
14.Wider Societal Implications
7.Executive Summary
REALITY has focused on developing industrially relevant innovative design techniques, methods, and flows for the design and analysis of energy-efficient self-adaptive SoCs. The tackled challenges have included benchmarking the impact of the latest 32nm CMOS process manufacturing variability at all abstraction levels, from device to System on a Chip level, while developing approaches to compensate their negative impact in the design of final products. REALITY has resulted in a number of first time conclusions.
For a first time, a full statistical characterization of an ARM926 core has been achieved. ARM cores are the flag-ship of the European embedded computing industry. These are very popular microprocessors found are at the heart of billions of battery operated devices worldwide. There is no doubt that understanding the impact process variations at advanced process technologies in such popular devices will provide key competitive advantage to European design industry.This is indeed the case, especially now that most European semiconductor manufacturing capabilities are being outsourced to companies outside the European Union.
To achieve this, much R&D effort had to be put in place along these two and half years of project to understand its impact from device to system. For the first time, full scale 3D simulation of statistical variability associated with metal gate granularity and the corresponding metal work function variations has been carried out to clarify the magnitude of statistical variability in 32 nm CMOS transistors with high-k/metal gate stack. It has been observed that for these devices the metal granularities can double the variability if the metal grain size becomes comparable to the transistor dimensions.In addition, technology has been developed to simulate the statistical aspects of variability degradation associated with reliability and ageing effects such as Negative and/or Positive Bias Temperature Instability.
Using such popular ARM core, REALITY has provided deep understanding on the way timing, leakage and dynamic power and especially their statistical response under process variability correlate at the product level, both for local (within die) and non-local (above die) variations.The traditional corner analysis has been be benchmarked with innovative statistical analysis techniques. To achieve a high accuracy of the statistical models, complex mathematical methods and algorithms have been carried out within the project.
Using the ARM core as driver, REALITY has confirmed that the SRAM components are responsible for more than the half of the variations on critical path timing. Hence, concluding that Statistical Timing Analysis (SSTA) flows, widely promoted by the Electronic Design Automation Industry, that assume predictable timing response from these components may lead to over-optimistic conclusions. Much focus has been placed by both state-of-the-art and EDA vendors on the logic while the variability challenges remain in the memories themselves. That said, these techniques are simply not sufficient to predict silicon response at design time. For that purpose REALITY has been also first in deploying a holistic statistical characterization flow including memory analysis.
In the context of reliability, life-time prediction for aged circuits must consider process manufacturing variations at and their evolution over time. With a novel flow integrating manufacturing variations and ageing effects for mixed- signal circuits, the REALITY project has been also first developing a CAD environment that allows designers to make more accurate estimations and thus make circuits more energy and cost efficient.
Finally, REALITY has also for first time evaluated the impact of process variation in SW level metrics showing process variability is not only a concern for HW but for SW as well. It has concluded that variability affecting multi-core multimedia platforms makes it hard to guarantee a certain QoS from the running application’s functionality. The speed variations across the cores cause sub-optimal and platform-dependent parallelism. REALITY has developed an approach to compensate this by using a smart allocation of the workload at run-time, hence also at the SW level, and obtaining an improvement of QoS by 20% and energy consumption by 15% while obtaining better platform predictability.
For that purpose, different circuit design techniques for system adaptation have been investigated, among them Adaptive Body Biasing (ABB). REALITY has shown that even though the possible compensation range in speed up due to ABB is significantly reduced compared to the previous node, it remains still available at 32nm. The technique has been validated on the ALU design of the ARM core using specially characterized commercially available libraries.
In summary, REALITY has been a first-of-its kind project that has linked process technology and system design. Efforts invested in REALITY will pay-off in the many years to come as it has been the first public funded R&D effort that has successfully bridged the traditional gap between electronic design and manufacturing, key for future nanoelectronics. REALITY has been able to identify the technical ingredients of the model needed for a scalable eco-system between semiconductor foundries, fab-less/fab-lite design industry and electronic design automation companies.
8.Summary description of the project context and objectives
8.1.1.Concept and project objective(s)
Why is this project needed?
It is becoming common knowledge that the progress and scaling of CMOS technology is hitting several brick walls. The most obvious is the fact that due to scaling the dimensions of silicon devices are approaching the atomic scale and are hence subject to atomic uncertainties. According to the ITRS roadmap, this is becomes of concern at 45nm, and will become critical at the 22nm technology node and below. It is also well-know that other ‘brick walls’ are likely to impair technology scaling even before this. Lithography resolution, photo resist and electrical field limits (due to power supply voltage fluctuations, thin oxide breakdowns, etc.) are already critical issues for 65nm and 45nm technologies. However, to achieve the predictions of Moore’s Law, whilst increased transistor density is of course important, the next key challenge is to optimally integrate foundations such as process technology into the architecture/micro-architecture and system tool flows. Such integration will drastically reduce development cycle and NRE costs, allowing tighter time-to-market windows, and achieve high yield to compensate for the soaring economic investments necessary to develop the next generation nanometre technology nodes and build their manufacturing facilities. Such a trend will dictate a deep rethinking of system architectures and design methodologies.
This project addresses all the issues above: soon it will not be possible to design systems using current methodologies and techniques and soon, if not already today, we will be confronted with the design reality to realize reliable systems with unequal, variable, and unreliable components.
Technology scaling has traditionally offered advantages to embedded systems in terms of reduced energy consumption and die cost as well as increased performance, without requiring significant additional design effort. Scaling to and past the 32 nm technology node brings a number of problems ‘(“technology gaps’) whose impact on system level design has not yet been evaluated. Random intra-die process variability, reliability degradation mechanisms and their combined impact on the system level parametric quality metrics are prominent issues that will need to be tackled in the next few years.
Figure 1 (a) 3D simulation of 35nm MOSFET in presence of random dopants and LER. / (b) ST measurements of the potential distribution in a similar device (Fujitsu).Statistical variability introduced predominantly by discreteness of charge and granularity of matter has become a major limitation to MOSFET scaling and integration [[1],[2],[3]]. It already adversely affects the yield and reliability of SRAM [[4]], causes timing uncertainty in logic circuits [[5]] and by slowing down the scaling of the supply voltage exacerbates the on-chip power dissipation problems [[6]]. Figure 1 illustrated the variability 35 introduced by random discrete dopants and line edge roughness in a 35 nm gate length MOSFET.
Progressive scaling of CMOS transistors, as tracked by the International Technology Roadmap for Semiconductors (ITRS) [[7]] and captured in Moore’s law, has driven the success of the semiconductor industry, delivering larger, faster, cheaper circuits. Silicon technology has now entered the nano-CMOS era with 40nm MOSFET’s in mass production at the current 90nm ITRS technology node [[8]] and sub-10nm transistors expected at the 22nm technology node, scheduled for production in 2018. 4nm transistors have already been demonstrated experimentally [[9]], highlighting silicon’s potential for scaling beyond the end of the current ITRS.
Figure 2 Technology-design interdependence Challenges facing the semi-conductor industry (G. Declerk [[10]])
However, it is widely recognized that variability in device characteristics and the need to introduce novel device architectures represent huge challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits (Figure 2). This will in turn demand revolutionary changes in the way in which future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate this increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designers
These fluctuations stem from the fundamental discreteness of charge and matter and the statistics of small numbers such as random discrete dopants (Figure 3 and Figure 4), line edge roughness and oxide thickness fluctuations [[11]]. While intrinsic parameter fluctuations and resultant device mismatch have hitherto affected only analogue design, they now challenge the power consumption, yield and reliability of digital circuits [[12]]. One of the first digital ‘’casualties” is SRAM, which occupies significant real estate in current System On Chip(SoC) devices [[13]]. Figure 5 illustrates the random dopants induced distribution of static noise margin in an ensemble of SRAM cells of various cell ratios at the transition between the 90nm and 65nm technology nodes.
Figure 3 Random discrete dopants in a 35nm MOSFET from the present 90nm technology node. /
Figure 4 Corresponding variations in the current-voltage characteristics of 200 transistors wit h different dopant distributions /
Figure 5 Corresponding distribution of the static noise margins in 6T SRAM cells
It is expected that there will be no single replacement for conventional MOSFET’s and that disparate device architectures will coexist and compete. This adds to the design challenges associated with increasing device and circuit variability.
What do we wanted to achieve with this project?
The objective of this project is to develop design techniques and methodologies for real-time guaranteed, energy-efficient, robust and adaptive SoCs, including both digital and analog macro-blocks. The technological challenges to be tackled are:
(a)how to cope with increased static variability and static fault rates of devices and interconnects;
(b)How to cope with increased time-dependent dynamic variability and dynamic fault rates.
(c)build reliable systems out of unreliable technology while maintaining design productivity;
(d)Deploy design techniques that allow technology scalable energy efficient SoC systems while guaranteeing real-time performance constraints.
In order to tackle these challenges we focus the R&D effort along two main axes:
Analysis techniques for exploring the design space, and analyzing of the system in terms of performance, power and reliability of manufactured instances across a wide spectrum of operating conditions (thermal, noise, age).
Solution techniques (design time and/or runtime techniques) to mitigate impact of reliability issues (seen as time-dependent variability aspects) of integrated circuits, at component, circuit, and architecture and system (application, software) design.
Classical versus variability aware simulation
The technique most often employed to face variability and reliability is to introduce a heuristic slack-based approach to the classic ‘corner’ analysis (also termed guard banding, or worst-case design). More advanced statistical analysis methods might be used instead. Statistical Static Timing Analysis (SSTA) techniques have recently been introduced in industry for the identification of the timing critical paths in standard cell-based circuits and SoCs under process and environmental variations, and for an early estimation of the impact of variability on parametric timing yield during the sign-off verification phase. Major EDA vendors provide commercial tools supporting this trend. SSTA may properly identify and allow the optimization of cell sensitivities with respect to variations, allowing inherently statistical optimization methods instead of worst-case analysis. In this way, it will be possible to increase the design performance without introducing excessive pessimistic margins, thus taking full advantages of technology scaling. 15% performance [[14]] and 20-30% power reduction [[15]] at target timing yields are reported in the literature.