1Readout Electronics for ECAL
Overview
The ECAL system requires low power, compact, large channel-count readout electronics. The center piece of the system is the KPiX ASIC, a 1,024 channel integrated circuit with front-end processing and digitization. The KPiX ASIC will be bump-bonded directly onto Si-detectors in order to eliminate pitch-adapters or massive cabling. Figure 1 shows a view of the KPiX assembly. Up to 12 KPix/detector sets are interconnected using a flex-cable connected to digital concentrator boards located at the perimeter. About 50k KPiX ASICs are required to instrument the 500k channel ECAL barrel.
Figure 1: 1,024 channel KPiX ASIC bumpbonded to the detector.
To take advantage of the moderate occupancy in the ECAL and the 199 msec spacing between pulse-trains at the ILC, only signals above a programmable threshold are digitized and transmitted off chip before the next train arrives. Figure 2 shows a simplified block-diagram of one of the 1,024 channels on the chip. The detector signal is amplified and shaped and compared to a set of threshold voltages. Auto-range gain switching circuitry is included to achieve a total dynamic signal range of 15 bits. A signal exceeding the threshold is analog stored in an on-chip capacitor. Up to 4 events can be self-triggered and acquired in each of the 1,024 channels. That exceeds the minimum requirement of two during a pulse-train. The amplifier is reset before each beam crossing unless the signal exceeded the threshold, causing the resets to stop until storage of the signal is completed, equivalent to double-correlated sampling The analog stored signals of the selected gain range are digitized via 13-bit Wilkinson Analog-to-Digital converters (ADC). There is one ADC in each channel. Depending on the occupancy in a bunch train, up to 4k digitized events with associated time-stamps can be transmitted off chip via a single 25-Mb/sec output line. The KPiX is optimized to minimize IO’s. All the control and timing signals to configure and operate the KPiX are generated via an on-chip synthesized digital VHDL core. Only 4 signals are required to control and readout the ASIC, three of them single-ended, one differential. Power is minimized by reducing the current in the front-end during the 199ms bunch spacing by two orders of magnitude. The important feature is that the voltage remains at full value, only the current gets reduced. In that way, filter capacitors, on-chip of off, do not need to be recharged. On-chip calibration Digital-to-Analog converters (DAC) and associated control circuitry enable electronic calibration of arbitrary selectable combinations of channels. The gain of the amplifiers can be configured to accommodate a range of detector signal amplitudes. Circuits to compensate detector leakage currents are integrated on the chip.
The KPiX can be programmed to process positive or negative detector input signals. Neighbor triggering can be enabled via configuration to read out nearest neighbors of auto-triggered channels. This feature together with the above listed functionality enables the KPiX to be potentially used in other detector sub-systems, e.g. for the RPC’s and GEMS of the HCAL, and for the muon system RPC’s. In addition the chip can be configured to accept an external trigger instead of the on-chip channel-specific auto-trigger for use in e.g test-beams.
Figure 3: Simplified block diagram of one channel of the KPiX.
Status
A 2x32 channel KPiX was designed and fabricated in the TSMC 0.25um technology. All functions were included on the chip including the complete digital core to support the full 32x32 final version. A 64-channel initial prototype was chosen in order to reduce development cost driven by the chip fabrication cost which scales with the total area of the ASIC. Figure 3 shows the layout of the device. Test boards were designed and fabricated, the test setup was commissioned and software to operate the chip and analyze its performance was written and debugged.
Figure 3: 2x32 channel KPiX version
At this time the chip was evaluated for two separate application: the ECAL application (auto-triggering, positive detector signals, ECAL gain settings) and the GEM test-beam application (negative input signals, external trigger, GEM gain settings). In addition to input signals from external pulsers and the internal calibration circuitry, the chip was also assembled to a Si-detector and Am241 and Sr90 source signals were recorded. Those measurement results are currently being analyzed.
In the following table the driving design requirements and the current measurement status is summarized.
Specification / Required / Tested/MeasuredConfigurable gain switching / yes / yes
External Trigger / yes / yes
Calibration / yes / yes
Sparcified Readout / Yes / yes
Operating clock frequency / 25 MHz / 25 MHz
Auto-gain switching / Yes / yes
DynamicRange / 15 bit / > 14 bit
Noise (ECAL mode) / < 2,500 e / < 3,000 e
Max Signal (ECAL, 5 mm pixels) / 10 pC / > 10 pC
Auto Self-trigger / Yes / Yes
Cross-talk / < 1% / tbd
Power (for 1,024 channels) / < 40 mW / ~ 20 mW
Positive or negative input signals / yes / yes
Noise (GEM mode) / < 40,000 e / < 40,000 e
Nearest neighbor logic / yes / yes
Leakage current compensation / > 4 uA / > 5 uA
In Figure 4 a calibration measurement result showing the low and high gain auto switching are shown.
Figure 4: Calibration injection transfer function, low and high auto-select gain range response.
A prototype of the flex-cable interconnecting up to 12 KPiX/detector assemblies has also been designed and is waiting to be fabricated. Tests to bump-bond KPiX chips to detectors are in progress.
Plans
Evaluation of the 64-channel version is still in progress. Additional performance tests are planned, e.g. more cross-talk and noise measurements, forced neighbor trigger analog performance, and more measurements using different kind of radiation sources.
A measurement setup has been completed for a test-beam investigating the GEM mode. In June 07 the performance of the device is expected to be measured in the test beam.
Layout changes to further reduce voltage drops on power traces on the chip and cross-talk between channels have been completed. The current plan is submit another 64-channel device with subsequent evaluation before submitting the full 32x32 channel KPiX.
The current KPiX will be assembled to a detector and integrated with a flex-cable to investigate system performance.
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