Project 11
Common Emitter, Common Collector Amplifiers with Current Source Biasing
(designed for two lab periods)
Objective: This project will focus on the use of BJT current mirrors to provide the DC biasing for Common Emitter and Common Collector amplifiers, two of the primary BJT amplifier stages. The design of each amplifier type (CE and CC) to achieve a specific design goal using current biasing will be examined. The frequency response and feedback adjustments will also be investigated.
Components: 2N2222 BJT
Introduction:
One of the primary differences between discrete and integrated amplifier design is the use of resistors. This change in design approach is based primarily on two major factors. First, resistors require a large amount of semiconductor "real estate", especially when compared to active devices, therefore the use of active devices in place of resistors is desirable. The second factor relates to the ability to obtain specific resistance values in the integrated circuits. While very precise resistance ratios can be obtained, processing, fabrication, and material parameters combine to make exact ( 1% tolerance) individual values very difficult and expensive to obtain. These two problems have lead to a change in the DC bias design for both analog amplifiers and digital circuits. This project will examine the use of a BJT current mirror, as discussed in Project 8, to provide the DC bias for a Common Emitter and a Common Collector amplifier. The actual AC amplifier analysis and design is the same for both discrete and integrated circuits with the related change in the biasing network. The students are referred to Projects 9 and 10 for detailed discussions on the AC analysis of the two amplifier types. A discussion of the changes associated with current biasing will be the focus of this project.
Figure 11-1 shows the Common Emitter Amplifier with the biasing current source in the emitter branch. The collector current is approximately equal to the bias current and basically independent of beta. This removes the need to try and provide a beta stable bias circuit using base resistors in conjunction with an emitter resistor. The designer is then allowed to adjust RB to improve the input impedance without having to worry about the relationship between RE and the base bias network.
The small signal gain for this circuit is:
which shows how RB can be adjusted to improve the coupling of the source signal into the amplifier and thus increase the overall voltage gain. Note that in the gain equation is the effective source resistance of . Feedback can still be provided by placing a resistor (RE) in series with the current source by-pass capacitor (CE).
A Common Collector amplifier with current source biasing is shown in Figure 11-2. The biasing current is again included in the emitter branch. The collector current and RB can be adjusted effectively independent of the specific transistor beta in order to meet design input, output, and gain specifications. Notice that RE has also been eliminated from the circuit through the use of current biasing. Again, as in the Common Emitter amplifier, the voltage gain for the Common Collector amplifier is a strong function of the value chosen for RB. As seen from the small signal gain equation:
The gain approaches the theoretical limit of 1 for a large range of loads when . The current source impedance and the transistor output impedance are represented by r01 and r02 respectively in the above equation and represents the effective source resistance of .
Figure 11 - 1: Common Emitter Amplifier with Current Source Biasing
Figure 11 - 2: Common Collector Amplifier with Current Source Biasing
Design:
1. Design a common emitter amplifier as shown in Figure 11-1 with the following specifications:
A. use a 2N2222 BJT and a 12 volt DC supply
B. midband gain VO/VS 50
C. low cutoff frequency FL between 100 Hz and 200 Hz
D. input impedance as seen by the source 5 k
E. VO symmetric swing 2.0 volts peak (4 V p-p)
F. load resistor RL = 1.5 k
G. source resistance RS = 50 (this is in addition to the function generator's
internal resistance)
H. Widlar current mirror to meet bias current specifications. You may assume you have a ± 12 V supply available.
2. Determine the value of RE to place in series with the CE shown in Figure 11-1 in order to provide feedback for the CE amplifier designed in step 1. The new voltage gain should be 5 while all other specifications remain unchanged.
3. Design a common collector amplifier as shown in Figure 11-2 with the following specifications:
A. use a 2N2222 BJT and a 12 volt DC supply
B. midband gain VO/VS 0.7
C. low cutoff frequency FL between 100 Hz and 200 Hz
D. input impedance as seen by the source 10 k
E. VO symmetric swing 3.0 volts peak (6 V p-p)
F. load resistor RL = 250
G. source resistance RS = 50 (this is in addition to the function generator's
internal resistance)
H. Widlar current mirror to meet bias current specifications. You may assume you have a ± 12 V supply available.
Lab Procedure: (steps 1 and 2 may be omitted if done prior to this lab period and the same BJTs are used)
1. From the digital curve tracer, find the value of DC and AC at the designed Q-point of the CE amplifier. Remember DC = IC/IB and AC = IC/IB. How do the two values compare?
2. Determine the values of hoe and hie from the digital curve tracer. The slope of the transistor IC-VCE curves in the active region is hoe. Find hie by looking at the base-emitter junction as a diode on the curve tracer. The tangent slope of the IB-VBE curve at the IBQ point is 1/hie.
3. Construct the CE amplifier of Figure 11-1 as designed in step 1 of the design section. Remember RS is installed in addition to the internal 50 resistance of the function generator. Verify that the design specifications have been met by measuring the Q-point (IC and VCE), midband voltage gain, and peak symmetric output voltage swing. Note any distortion in the output signal.
4. Observe the loading affect by replacing RL first by 150 and then by 15 k. Note any changes in the output signal and comment on the loading affect.
5. Use computer control to record and plot the frequency response. Find the corner frequencies and bandwidth to verify that the design specifications have been met.
6. Measure the input impedance seen by the source [look at the current through RS and the node voltage on the transistor side of RS] and the output impedance seen by the load resistor [look at the open circuit voltage and the current through and voltage
across RL = 1.5 k]. Verify that the input impedance specification has been met.
7. Now insert the RE determined in step 2 of the design section in series with the by-pass capacitor CE to form a series-series feedback configuration. Measure the Q-point and midband voltage gain. Note any distortion in the output signal.
8. Repeat steps 4 - 6.
9. Construct the CC amplifier of Figure 11-2 as designed in step 3 of the design section. Remember RS is installed in addition to the internal 50 resistance of the function generator. Verify the amplifier operation by measuring the Q-point and midband voltage gain. Monitor the output on the oscilloscope to make sure the waveform is not clipped. Note any distortion in the output signal.
10. Adjust the input signal level to get a 3.0 volt peak symmetric output voltage swing.
11. Determine the midband current gain IL/IS [measure IS by looking at the current through RS] What is the overall power gain?
12. Observe the loading affect by replacing RL first by 50 and then by 750 . Note any changes in the output signal and comment on the loading affect.
13. Repeat steps 5 and 6.
Questions:
1. Could these circuits be supplied with a current source without using both positive and negative DC sources? Explain your answer.
2. What are the advantages/disadvantages of using a Widlar current mirror instead of one without the RE in the load branch?
3. Why is the current source bypassed for the CE amplifier but not for the CC circuit?
4. What value of load resistance results in maximum voltage gain? What load resistance results in maximum power transfer to the load?
5. Compare the Lab measurements for each amplifier to the theoretical predictions (such as those obtained using PSPICE®). Note how increasing the feedback in the CE amplifier affects the gain, bandwidth, and input and output impedances.
6. Compare the results of the current gain found in Lab Procedure 11 with the maximum possible gain of +1. Comment on any differences.
7. What other method could be used to measure RO for these circuits?
8. Why is the value of FH measured in the lab generally different from (lower than) the value of FH determined using PSPICE® or manual calculations?