Proceedings of the KGCOE Multi-Disciplinary Engineering Design Conference Page 1

Project Number: 08311

FPGA based multi-pupose Driver/data acquisition system

Steven Fastrow –CE
Andrew Fitzgerald -CE / Brian Pinkham – EE
Murtuza Quaizar –EE
Corey VanBlarcom -EE

Proceedings of the KGCOE Multi-Disciplinary Engineering Design Conference Page 1

Abstract

The objective of this projectis to develop an integrated system solution that has the capability of enabling PC applications to acquire and control real time data through a re-configurable FPGA system. This project will enable future capability that canbe defined and driven by PC applications. This systems consists of three major functions, a custom designed circuit board complete with data acquisition, and drivers, reconfigurable FPGA, embedded PowerPC processor running an HTTP server. The PowerPC, processor will allow the versatility of running diverse software applications while at the same time taking advantage of the custom designed, hardware system.

introduction

Thissystem enables PC applications to drive electronic Data Acquisition and drivers forapplications, including ASIC testing and robotic environmental controls. For ASIC testingthe system must be fast, complete, trouble-free, and economical.

For robotic applications, the device must be robust and accurate to acquire various environmental data, and drive a wide array of onsite applications.

Therefore the project P08311, as a revision to the work of P07301 will contribute significantly to the growing field of data collection, by creating systems that are capable of acquiring digital and analog inputs and driving digital and analog inputs.

Figure 1: A Block Diagram of the System

The system is designed to be operated over a Web Browser via Ethernet, using Virtex-4FX platform; an embedded PowerPC with FPGA. This will enable future functionality that can be defined though high level application.

Thissystem hasthe versatilityto acquire analog voltage inputs and TTL/CMOS digital inputs to be implemented by an FPGA based multi-purposed DAQ system. The final implementation can support a robotic platform, and serve as viable testing environment for testing digital ASICs.

The objective of the design is to meet the desired specifications and build a working prototype that includes a printed circuit board. The working prototype will include analog input with signal conditioning, digital I/O, analog current output, analog voltage output, and controlling and interfacing software.

Nomenclature

ADC: Analog to Digital Converter

ASIC: Application specific integrated circuit

DAC: Digital to Analog Converter
DAQ: Digital Acquisition

DATA ACQUISITION: The inputs to the System

DRIVER: The output of the FPGA based Data Acquisition

ELF: Executable Linker File

FIFO: First in First Out

FPGA: Field Programmable Gate Array

FTP : File Transfer Protocol

GUI: Graphical User Interface

HTTP: Hyper text transfer protocol

JAVA: Programming Language

Ksp/s: Thousands of Samples per seconds

I/O : Input-output

PC : Personal Computer

PCB: Printed Circuit Board

PIC : programmable integrated circuit

QNX : Supported Operating System for Xilinx ML403

OS : Operating System

RAM: Random Access Memory

MUX : Multiplexer

TTL/CMOS: Transistor-transistor Logic

VXWORKS: Supported Operating System for Xilinx ML403

XilCore: Supported Operating System for Xilinx ML403

NEEDS

The goal of the FPGA Driver/Data Acquisition system was to satisfy the needs of two existing customers. Professor George Slack from the department of Electrical Engineering at the KateGleasonCollegeneeds to utilize the DAQ system to record and output analog data in a robotic platform, and Dr. Marcin Lukowiak, from the department of Computer Engineering at the KateGleasonCollege, needs to test an ASIC with digital inputs and outputs.

It was planned that the system was to be presented in the form of a GUIto be run on a PC host, backed by a supported hardware. The FPGA based platform that Professor Lukowiak had recommended, was a Diligent Development board.

SPECification

The hardware wasoriginally designedwith 24 analog voltage inputs, 16 digital inputs, 8 Analog Voltage Output, 8 Analog controlled Current Output and 16 digital outputs. The analog signals had to accept voltage levels from 0 to 12 volts, with a sampling rate of 20Ksp/s. The digital signals had to be processed at the fastest possible rate. The system was also required to have a run time of 1 hour off an internal rechargeable battery.

The above specifications werenegotiated and wereredefined as the development process progressed. The battery capability was eliminated from the project, as it required a great deal of engineering time and had minimum impact on the final presentation of the system.

The Development board that was selected was the Xilinx Board for its sufficient number of I/O pins, its small and concise size, and its technical support from the manufactures. The digital inputs were reduced from 16 digital inputs and 16 outputs to 12digital inputs and 12 digital outputs to meet the speed specification.

The interface to the PC-Host changed from a GUI interface to a system interface over a web browser. This change was motivated bytime constraints in implementing a JAVA application communication protocol for PC-Host and development board.

Table 1: Specifications for the final deliverables for the DAQ system

CONCEPTS

Figure 1 showsthe system layout including each of the inputs and outputs of the systems at the margins, while at the center was the FPGA. The design was considered to have a hardware that would interface with the environment, and support the activities and functions of the FPGA which would reside as the center of the project.

The analog inputs and outputs, and the digital inputs and outputs, and power management was developed by the Electrical Engineers. And the FPGA, embedded processor and the user interface was designed by the Computer Engineers.

DESIGN OF HARDWARE

Analog Inputs

The active analog Filter was one of the most important hardware stages in order to ensure signal integrity for the analog inputs. The inception of the input end of the Analog design was tested against three different types of implementations schemes.

The first was to multiplex or MUX the input, and then do the filtering and signal condition between the multiplex and the ADC. The second implementation idea was to filter the input and then multiplex the input signals directly to the ADC. Thirdly, the idea to use a micro controller to take the place of the multiplexer, and serially connect the Analog input to the FPGA, while doing the ADC within the PIC.
The first idea was eliminated due to propagation delay. The idea behind the micro controller was a plausible alternative to replacing the ADC, DAC, MUX and the COUNTER. However this idea was also dropped due to the steep learning curve associated with the implementation of this method. The third idea, which was similar to the first, required for the filtering of the analog input to occur before the MUX, rather then between the MUX and ADC. It was chosen for its straightforward solution.

Decision was made to design for a higher order low pass filter. The motivation for this design was the needed capability of meeting the customer’s specification to sample data at 20Ksp/s. According to the Nyquist theorem, to sample at 20KHZ, no more than a 10KHZ signal was expected to be at the input of the ADC. Any signal of significant amplitude that was passed through with a frequency greater then 10KHZ, would alias and potentially distort all other inputs from that channel. Therefore, a steep 3dB cutoff was designed with an earlier frequency roll off.

Figure 2a: PSPICE schematic view of the Low pass Chebyshev filter of the 4th order

A Low pass Chebyshev filter of the 4th order, shown in Figure 2a. Cutoff frequency was designed at approximately 1.4K Hz, with a ripple of 0.01dB and a 40dB per decade roll off. The Filter consisted of two 2nd order SallenKey circuits, and voltage attenuating circuit at the output. The recorded implementation of the filter is shown below in Figure 2b.

Figure 2b: Voltage input (top), and filtered voltage output (bottom)

The output from each of these 16 filters goes into one of two 8 channels multiplexers (ADG408). These multiplexers were used to switch between all 16 input channels and were chosen for their fast switching speeds (250ns) and low ‘Turn On’ resistance (<100 ohms).

Themultiplexers are addressed by the output of one 4 bit binary counter, which is incremented by the FPGA. This was done to minimize the number of connections that needed to go to the FPGA.

Figure 3: Complete design of the Analog to Digital Conversion

The output from the multiplexers enters the inputs of two analog to digital converters (ADC121S101). The voltage values read at these inputs is then converted into a 12 bit binary representation and transmitted to the FPGA serially at a sample rate of 500KS/s.

The complete conceptual design of the analog to digital conversion was implemented, and is shown in Figure 3.

Analog Outputs

The output to the data acquisition board had16 channels. Of those channels, 8 are allocated for analog current output, seen in Figure 4a. Those current outputs ranged from 0-20mA given an inputof 0 to 5 V from the FPGA board, shown in Figure 4b

Figure 4a: PSPICE schematic view of the Output Current Source

Figure 4b: Current output (bottom) Vs. Voltage in (top)

The other 8 channels were for the Voltage output circuit, shown below in Figure 5a,and took similar voltage level from the FPGA and scaledit to 0 to 12 volts.

Figure 5a: PSPICE schematic view of the Output Voltage Source

Figure 5b: Voltage input (channel 1), and scaled voltage output (channel 3)

Digital Inputs and Output

The Digital input for the Data acquisition system was taken from an ASIC and other various DAQ applications. The inputs were meant to be highly modular and fully reconfigurable giving the user full control of what is designated to be an input or output. The 12 digital inputs and 12 digital outputs are interchangeable and reconfigurable. The digital inputs and outputs are directly tied into the FPGA, meeting the specification for having the signals be as fast as the electronic devices were capable.

Power Management

Power was supplied from an ATX power source. The supply, was rated at 250 W, it supplied all the voltages needed for full functionality of the FPGA Multipurpose system.

Though the power requirement was reduced significantly from having to design a board with a rechargeable battery to using an ATX power supply, power management was still a key issue.

The option to select a number of different voltage outputs for the digital inputs and digital outputs was made available on the hardware system. The Voltages were selected using a jumper at the output of a specified voltage. These voltages were floating at the end of a voltage regulator, until a jumper closed the loop on the requested voltage.

PCB Board

The Printed Circuit board layout was done using the PCAD tool software. The final revision of the board, was a 12 ½ x8 ½ in with 4 layers, and a one ounce copper.

Figure 6: PCB implementation of the hardware design

The top and bottom layer served as the majority of the routing layer, Layer 2 was created as the power plane for the -12V, +12V, and +5V, and Layer 3 was designed to be the Ground plane. The 4 layer board solution was expensive but necessary for signal integrity and noise consideration.

The Bottom right corner of the board has 2 rows of 32 pin headers that were designed to mate with the Development board from the top.Finally the left most connector was an open connection for the ATX power supply.

The board was done with experienced hands and was reviewed by an outside firm that generously gave their time to reviewing our board.

DESIGN OF FPGA PLATFORM

Software-Hardware Co-Design

This project offered a unique challenge to the team, since no one had previously developed code to support both the software end, which included the embedded processor, and the hardware end, which was the FPGA.

Development Board

The FPGA based Development boardthat was selected had the most features, support, and minimal size. The Diligent Development Board, which was favored by the customer, had similar favorable features, but lacked support. Therefore the team decided to go with another FPGA platform, which would have technical support, sincethere was little to no prior experience in programming for a Software /Hardware co-design.

Figure 7: Top view of the Development board Xilinx ML403

The team chose the Xilinx ML403, for its numerous and winning features. It had an Ethernet port, USB, 64 I/O pins, compact flash, LCD screen, LCD diodes, and buttons and switches which were useful when debugging.

Operating System

Time and resources was spent in selecting the most appropriate Operating System to support the communication line between the PowerPC processor and the FPGA. Before deciding upon the final operating system,it was evaluated that three different operating systems, QNX, VXWORKS, andXilCore were viable to use.

Originally, the QNX operating system was to be used, because it came packaged with the Xilinx-ML403. However this operating system was difficult to use, and difficult to load on the development system and therefore had to be neglected.

Next VXWORKS was tried. In fact, though VXWORKSwas proprietary software of Wind River, Tom Wall, a representative from Wind River offered the use of the Operating systems without cost, as membersof the RIT community. He also offered much of his valuable time to help support VXWORKS on the Xilinx-ML403. But even with the efforts of Mr. Wall, the OS was unable to run on the development board successfully. After much speculation it was seen that though the Xilinx-ML403 claimed to be supported, the author of that application note never tested it on its platform, and VXWORKSwas abandoned all together.
XilCore was finally selected as the OS, which is a Xilinx kernel.

User Interface

A web browser was used to interface with the embedded processor using HTTP. This would require the user to load all their driver values (i.e. test vectors) on the compact flash, and control the configurations that they would want through a web page.

The original design of the system was to have a GUI implementation run on a host PC interface to the DAQ system. What it would have done was set up a FTP protocol using a JAVA APP, and allow the user to interface with the embedded processor (having it to run commands and etc), which in turn would have interfaced with the FPGA on the system.

FPGA Implementation

A FIFO data scheme to pass data to and from the FPGA, as shown in Figure 8. Specifically, 4 FIFO data buffers were used. The first pair of FIFOs was used for the digital inputs and outputs. The second pair of FIFOs was used for the digital information from the analog section’s inputs and outputs. For the read (input) FIFOs, data is passed in at a user specified clock rate. The information is then read in the embedded processor as fast as possible. This information is then written to the on board compact flash card via SystemAce controller. Information is passed from the output FIFO at the same user specified clock rate to the output pins on the development board.

The DAC and the Counter are both connected to the FPGA, which controls the timing and flow of its operation on the Analog end of the DAQ system

ANALYSIS & Evaluation

HARDWARE IMPLEMENATION

The initial analysis and evaluation of the functionality of the hardware was done on computer simulation (the filter system, and the voltage and current outputs). The next step was to bread board, including the multiplexers, DAC, and ADC.

The Altera Flex 10K was used to emulate the performance at the FPGA end of the Xilinx ML403 while the development board was being worked on, to test the performance of the system hardware.

Since Vivace Semiconductor allowed the use of their lab and equipment, thepurchaseof surface mount components as small as 0805 for the final implementation was a feasible design improvement. .

There was also the limited resources of the development system that had to be considered. The Development project was constraint with an original budget of twelve hundred dollars. However, since most of the cost had to be budgeted for the development board and the creation of the PCB, the team had half the amount of the original budget to work with.

Figure 8: The FIFO algorithm implementation for the FPGA

Special interest was take in insuring solid connections between the supported hardware and the development board, by using SAMTEC parts, which had gold planted pins and connectors.

FPGA/OS IMPLEMENATION

Implementation on the software end was trying to get the embedded PowerPC processor to establish a communication link to the FPGA, as shown above in Figure 9. Doing so required the need to get through much of the convoluted operations and workings of the development board. Due to a manufacturers defect, the software that came with the development board, EDKv9.2, didn’t generate code to talk with the peripherals of the system. The older version of the same software, EDKv8.2 was then reverted, which was used to generate the ELF file containing the code for the embedded processor, while still using EDKv9.2 for its efficiency in compiling the bit stream to program the FPGA.