Engr434Lab Exercise #5

Parasitic Extraction and Re-Simulation

Revised 4/30/2006

Note: For 2007, must choose which method for simulation (symbol mod vs. netlist mod)

Objective

The goal of this lab is to take your D Flip-flop from Lab#4, extract the parasitic values from the layout, and re-simulate to see what effect these parasitics have on circuit performance.

Design Flow

The general design flow we are using is shown below. The portions we will do today are bolded.

  • Initial design
  • Capture the design as a schematic
  • Create a symbol of your design
  • Create viewpoints for downstream applications
  • Create a testbench circuit
  • Create a netlist for simulation
  • Simulate your design to verify operation
  • Layout a cell for this design (IC station)
  • Verify layout
  • Check for layout rule violations (DRC)
  • Check layout against schematic (LVS)
  • Verify circuit operation including layout parasitics
  • Extract parasitics and back annotate data base
  • Re-simulate

Lab 5:Step-by-Step

In this section, you’ll complete the following steps:

  • Status check
  • View your D Flip-flop netlist
  • Open your layout and schematic
  • Extract your post-layout netlist
  • Simulate your new circuit

Status Check

At this point, you should have your schematic and layout done for your D Flip-flop. Your layout should pass DRC and LVS. In addition, you should have simulation waveforms that verify the correct logic operation of your circuit. You need to have the following two items precisely measured from your simulation:

  • Delay times (measured at the 50% level) for Clk to output low-to-high, and Clk to output-high-to-low with no load on the output.
  • Rising and falling times (measured at 10%, 90%) for your output with no load.

It is imperative at this point that all of the following are completed satisfactorily with no errors. Carefully observe any warnings and point these out to the teacher or lab instructor for clarification:

  • Schematic check
  • Symbol check
  • Layout DRC passed
  • Layout LVS passed
  • Port labels placed on all your input and output signals, as well as VDD and GND.

View Your D Flip-flop Netlist

Step 1: First you will view your netlist created when you simulated your D Flip-flop in Lab#2. The netlist is located one directory down from where you start Mentor Graphics. For example, if you named your D Flip-flop in Lab #2 dflop, your netlist filename will be dflop/dflop.src.net To view the contents of this file, at the Unix prompt type:

more dflop/dflop.src.net

Open your Layout and Schematic

Step 1: Navigate to the same directory you started Mentor Graphics from previously and open your layout by typing mentor at the Unix prompt. Select option 25, IC Station – IC, and press Enter.

Step 2: Select Open from the Session palette, navigate to your design, and click OK.

Step 3: Select the green ADK Edit button from the IC Palettes menu.

Step 4: Select the SDL > Open button from the ADK Edit palette to open the logic source.

Extract Your Post Layout Netlist

Now that you have completed your layout and confirmed it is correct, it is time to extract the parasitic values from your actual layout. This will give you a spice netlist of your layout complete with one or all of the following options: resistance, parasitic capacitance, and coupling capacitance. For the extraction process you will use the tool Calibre Interactive – PEX.

Step 1: In the IC Station menu bar at the top of the window, select Calibre > Run PEX. This will launchCalibre Interactive – PEX.

Step 2: If this is your first time running Calibre Interactive – PEX, you will need to create a new runsetwhich is a file created that stores your configuration information. Subsequent runs of Calibre Interactive – PEXcan then use this previously saved information so you don’t have to enter it again. If a menu comes up asking you for a runset file, click Cancel.

Step 3: Note that any button that is Red needs to be configured. Green buttons have valid information (it may not be what you want, but at least it is valid). Begin by clicking the red Rules button and setting the rule file and working directory. The Calibre-PEX Rules File box should be set to: $ADK/technology/ic/process/ami05.calibre.rules

Your entry should turn green when you finish typing.

Step 4: Click the Load button.

Step 5: Click the red Inputs button. The Layout tab should be set correctly by default and you can ignore the H-Cells tab. Click on the Netlist tab and set the Files: box to $MGC_WD/design/<design>.src.net

where design is the name you assigned to your schematic. This entrypoints to the netlist that was created previously in Lab #2. For instance, if your design is named dflop, you would set this field to:

$MGC_WD/dflop/dflop.src.net

Step 6: Now, select the Outputs button on the left. At the top, the Extraction Type should be Transistor Level and C (Lumped C + coupling caps on the pop-down menu). In other applications, you can choose one of the following types of extraction:

  • Distributed RC network with coupling capacitors
  • Distributed RC network without coupling capacitors
  • Lumped net capacitance with coupling capacitors

Step 7: In the Netlist tab, you can setup the output format and file name. For our purposes, choose ELDO as the Format: and choose Source in the Use Names From: field. Leave the File: field as is.

Step 8: Next, choose Setup > PEX Optionsfrom the menu bar. In the Netlist tab, click the Ground node name: check box and enter GND. In the LVS Options tab, set the Recognize gates:check box to All. Also, make sure that VDDis one of the Power nets: and GND is one of the Ground nets:.

Step 9: Select File > Save RunsetAs…and enter $MGC_WD/<design>.runset as the file name. For instance, using the dflop example, you would enter $MGC_WD/flop.runset This savesyour current configuration information and saves you from having to enter all this information when you do another extraction later. Click OK.

Step 10: You should now be ready to perform the extraction, so click Run PEX. If a popup window asks to overwrite the layout file, click OK.

Step 11: When Calibre has completed the extraction, a window will popup showing the top level of the extracted netlist. Notice that there may be up to two additional netlists which will be included into the top level (depending on the type of parameters you are extracting). The first will contain the RC networks and the second will contain the coupling capacitors. If the C (coupling capacitance) option was chosen, the top-level netlist will be the only one containing circuit specific parameters, and you should see a capacitance value from every circuit node to GND.

Simulate Your New Circuit

You have now created a new spice file that contains your circuit, plus the lumped capacitance values between each node and ground. In order to simulate this new file, several changes must be made to this and other files. Specifically, you will:

  • Go back into simulation mode with DA-IC
  • Modify your spice netlist file
  • Modify the simulation command file
  • Re-simulate

Step 1: Close any Calibre windows that are open and exit IC Station.

Step 2: Type mentor at the Unix prompt, and select option 23.

Step 3: Open your design schematic corresponding to the layout you just closed. Click the Simulation button in the schematic edit palette. Setup your simulation like you did in previous labs. Note that a simulation setup file may have been saved and all you need to do is verify that all the menus have the proper entries. If not, refer to lab#1 handout and set up the simulation, but do not yet run it.

Step 4: When you are finished setting up the simulation, make sure that you have the adk schematic_sim palette showing on the right (this is the palette that comes up when you click the green ADK Sim Palette button on the schematic sim palette). Open your extracted netlist file by selecting MGC > Notepad > Open > Edit… from the menu bar and navigate to your design by double clicking on your design component and selecting your netlist file entitled <design>.pex.netlist Click OK.

Step 5: Before the first .subckt statement, enter the following two lines:

.CONNECT GND 0

.global VDD GND

The first line connects the GND line to node 0, a convention that has been followed for a long time. The second line makes VDD and GND global parameters.

Step 6: Next, edit the .subckt line. Simply delete the VDD and GND parameters following your design name. For example, an example .subckt line for an inverter may look like the following:

.subckt inv4 GND IN VDD OUT

Delete the GND and VDD entries. Note that the name of the function in this case is inv4. Carefully note the order of the inputs/outputs listed in the .subckt line.

Step 7: Near the bottom of the file, append your function name unto the .ends line. For example, if your design is named inv4, this line should look like:

.ends inv4

Step 8: Below the .ends line, add an instantiation of your sub-circuit defined above. This will look like the following:

X_func1 IO0 IO1 IO2 ION function

where X_func1 is an instantiation of the sub-circuit function and IO0-N are a list of inputs and outputs that follow the same order specified in your .subckt statement. As in example, for a sub-circuit named inv4 with one input and one output, the line would look like:

X_inv4 in out inv4

Note that the capitol X is required to indicate to the spice simulator that this line is including an existing sub-circuit.

Step 8: The last thing to do before the netlist is ready for simulation, is to add stimulus lines. The easiest way to do this is copy-and-paste them from the testbench netlist. Open the notepad editor by selecting MGC > Notepad > Open > Edit and navigate to your test bench design by double clicking on your design component, double clicking on the ami05a directory with the dv on the left, and selecting your test bench schematic netlist file entitled <design>_ami05a.spi Click OK twice.

Step 9: Near the bottom of the netlist, identify the stimulus and instantiation lines. An example shown below is of a Pulse source, V1, a DC source, V2, and an instantiation of inv4:

V1 N$3 GND PULSE ( 0V 5V 10nS 1nS 1nS 20nS 50nS)

V2 VDD GND DC 5V

X_INV41 out N$3 inv4

You can enter these lines manually, or copy-and-paste them. I recommend the copy-and-paste approach if you have more them a couple of sources. Once you have copied these lines from the test bench schematic netlist, paste them to the end of the extracted netlist file. Verify that the order of inputs and outputs in the instantiation line matches those in the .subckt line near the top of the file.

Step 10: Add an ending statement at the end of your netlist: .end

Step 11: Save your modified, extracted netlist by selecting File > Save from the menu bar and then close the notepad window.

Step 12: The last step before simulation is to modify the commands file to point to your extracted netlist. From the adk schematic_sim palette, select Commands > Edit. Change the file in the .INCLUDE statement to point to your netlist file. The new line should look like:

.INCLUDE $MGC_WD/<design>.pex.netlist

Step 13: Save the commands file by selecting File > Save from the menu bar. Close the notepad window.

Step 14: You are now ready to simulate your extracted netlist. Select Simulation > Run from the adk schematic_sim palette. If there were problems running the simulation, open the transcript window by selecting Simulation > View Log, fix the problems, and re-simulate.

Step 15: View the results of your simulation by selecting Results > View.

METHOD II

Creating a New Symbol

The easiest way to use your extracted netlist in a simulation is to create a new symbol for it, which can then be placed in your testbench.

Step 1: Shut down IC Station if it is open and invoke DA-IC by typing mentor at the command prompt and select option 23. Click Open > Symbol in the session palette. Enter a name for your new symbol (something different than your original design) and Click OK. This will bring up a blank Symbol window.

Step 2: In the symbol draw palette, click Add > Rectangle, and then left-click and drag to create a rectangle.

Note: The size of the rectangle is not really important at this point as you can always edit it later.If you wish to edit it, right-click and choose Stretch: and then left-click inside the rectangle to shrink it to that point,or left-click outside the rectangle to stretch it to that point.

Step 3: Now, add the pins to your symbol by clicking Add > Pin in the symbol draw palette. In the window that pops up, choose the Pin Type:(either IN or OUT depending on the pin) then choose the Pin Placement: you want. Finally, enter the name of the pin and click OK. If you have several pins that will have the same Pin Type/Placement, then enter all their names and create all of them at once. Repeat this process until all the pins on your design have been placed.

Note: Generally, VDD and GND are considered to have a Pin Type: of IN.

Note: When placing the pins on your symbol you should refer to the .subckt statement in the extracted netlist to ensure you have placed all the needed pins.

Step 4: Once you are happy with the look of you symbol it is time to add the needed properties.First, Unselect All either by pressing F2 or using the corresponding stroke. Then right-click and choose Properties (Logical)… from the Add menu. This will bring up the Add Multiple Properties window.

Step 5: Enter the following two properties:

Property Name: ELEMENTProperty Value: X

Property Name: ASIM_MODELProperty Value: <your_design_name>

Leave everything else as set and click OK.

Step 6: Select a spot and left-click to place each property, and then click Text in the symbol draw palette to bring up the symbol text palette. Next, click Edit > Text Attributes in the symbol text palette. Now select the X which you just placed which brings up the Modify Property window. Set the Visibility Switch option to Hidden and click OK. This will make the ELEMENT property invisible when the symbol is placed in a schematic.

Step 7: Check & Save the symbol. Once it passes all the checks you can close the symbol and proceed to the next section.

Updating the Testbench

You can now use the new symbol in yourtestbench so that the extracted netlist created by Calibre will be simulated.

Step 1: In the session palette chose Open > Schematic and Browse to find your original testbench. Click OKto open it.

Step 2: Now, select the symbol from your original design by left-clicking it and then press the Delete key.

Step 3: Click Add > Instance in the schematic edit palette. Browse and find the new symbol you just created and click OK and then left-click in the schematic window to place the symbol. At this point you may need to redo some of the wiring in you testbench depending on how closely your new symbol matches the old one.

Simulate the New Circuit

Now that the testbench has the new symbol in it, you can set it up to use the extracted netlist and simulate your final design.

Step 1: With your testbench open, click the Simulation button in the schematic edit oradk schematic editpalette.

Step 2: In the adk schematic sim palette, choose Setup Other > Include to bring up the Set Include Paths window. Click Browse to find the top level netlist created by Calibre. Click OK.

Note: Do not include any of the other netlists created by Calibre as they are already included in the top level netlist.

Step 3: Now create a new netlist by clicking Netlist > Write in the adk schematic sim palette. This will create a new netlist of your design using the new symbol.

Step 4: Before proceeding with the simulation, you must ensure that the pin lists in the two netlists are the same.Calibre lists pins in the order it finds them in the layout where EldoNet lists pins based on their order on the symbol. As a result, these two pin lists are often different. To correct this you will need to edit the extracted netlist to match the one generated by EldoNet. The netlist created by EldoNet will be located at <design>/ami05a/<design>_ami05.spi where design is the name of your design. The Calibrenetlist is generally of the form <design>.pex.netlist and should be located in your working directory. Open both with your favorite text editor, or use the built in notepad by choosing MGC > Notepad > Openfrom the DA-IC menu bar.