New Mini-Series Tackles Today S Design Challenges

Mini-series_annouce.doc

[Barney and Ryan: Please run this where space permits. Also, would be nice to include a miniature picture of each e-letter, as we use in the Chip Design media kit. Call me with questions. Thanks. – JB]

New mini-series tackles today’s design challenges! Read the first of each three part mini-series in latest issue of these popular e-Newsletters:

FPGA Developer --> “The Real Story behind FPGA-Based Quality-of-Results (QoR)”

How can EDA tool vendors – like Mentor – balance the often conflicting needs of their users with the requirement of major hardware suppliers – like Xilinx? This mini-series presents all the viewpoints on this critical topic.

Wireless Chip Designer --> “Will analog-RF designs every truly fit into the SoC World?”

Imagine the magical worlds of Harry Potter colliding headlong with the physical world of Moore’s law. This is exactly what is happening as analog and RF designers are forced to work closely with digital and packaging engineers at smaller geometries. Read both sides of the important issues as EDA vendors – like Cadence - and hardware suppliers share their views.