MUON banks format
Abstract
This document defines the format of banks, including non-zero suppressed bank, zero suppressed bank and error bank,for LHCb MUON Detector. These 3 banks are raw data banks that canbe sent by the TELL1 to the DAQ.The non-zero suppressedevents are 20 times larger than typical zero-suppressed events and must therefore beused with very low rates during normal data taking.On detection of synchronization errors,error bank isautomatically generated. The use of error bank is limited to specialist during debugging.
Document prepared by:Chris Gong
Guido Haefeli
WalterRinaldi
1.Revision
Version 1.0, 2.2.2007
First definition of MUON banks
2.Introduction
Non-zero suppressed bank, zero suppressed bank and error bankare three kinds of raw data banks that can be sent by theTELL1 to the DAQ. They are defined referring to the banks format of ST[1] [2][3], and conform to the specification of the “Raw-data Format” [5].
The use of the non-zero suppressed data can be the verification of the data processing. The concurrentbank concept allows to readout non-zero suppressed and zero suppressed data for thesame event. On detection of synchronization errors,error bank isautomatically generated, which can provide detailed error information for the event with errors.
3.MEP format
3.1.Overview
The whole hierarchy of a MEP is shown in Fig. 1. Each MEP consists of a MEP headerand a number of events (this number is variable from MEP to MEP). The events consistof a MEP sub-header and several banks of data (the number of banks is variable fromevent to event). Each bank contains a bank header and the bankdata.
Figure 1: Overview of the hierarchy of the MEP.
3.2.MEP header
To give a complete picture of the information transmitted within a MEP, the MEPheader contents are shown here below. The definition of the data fields are given in [4].Remark that the MEP length field here is the total length of the MEP including the 3word MEP header.
Figure 2: The MEP header format is three words, the MEP subheader one word andthe Bank header two words long.
3.3.The MEP subheader
Each event in the MEP contains again a one word long MEP subheader. The definitionis also given in [4]. The length field here is the length of the event excluding the MEPsubheader word.
3.4.Bank header
The format of the bank header is defined in [5]. The length here is the length of thebank data excluding the padding at the end but including the Bank header of eightbytes.
4.Event info
This is the information collected after input synchronization of the data. Each PP-FPGA has a unique “Event info”, which consists of eight words. The first three words are used for eventidentification, synchronization check and to control processing options and are passedfor each event to the SyncLink-FPGA. At the last linking stage where the data fromthe four PP-FPGAs is merged, the three words are compared except for the half word in yellow. The OR result of PP_ODE_err from 4 PP-FPGAs acts as a part of MUON specific header employed by zero suppressed bank. If at the receiver synchronizer stage where the event info is build an error is detected,the total eight words are sent to the syncLink-FGPA such that an error bank with thecomplete error information can be generated.The full eight words of “Event info” are attached to the non-zero suppressed data.In Fig.3 the “Eventinfo” format is given.
Figure3: Here are the eight words of event info for the MUON.
4.1.Definition of the data fields
R Reserved bits for later use
BCN, 12 bit Bunch counter
Detector ID, 4 bit Each detector needs its custom synchronization but can be verysimilar. To avoid any confusion, the header gets a tag for the FPGA design used.
0x1 =VELO, 0x2 =ST, 0x3 =OT, 0x4=ECAL/HCAL, 0x5=MUON, 0x6=L0MUON, 0x7=L0DU, 0x8= L0PUS, 0x9= RICH,0xA=PS/SPD
Bank list, 8 bit For internal use:
Bit0 : info bank
Bit1 : cluster bank
Bit2 : adc values bank
Bit3 : raw bank
Bit4 : pedestal bank
Bit5-7: not used
Event information, 8 bit For processing internal use:
Bit0..4: not used
Bit5 : ecs trigger
Bit6 : data generator on
Bit7 : general error bit
L0-EvID, 32 bit L0 Event Counter
PP_ODE_err, 8 bit Overall error of 6 ODE data framesreceived by one PP-FPGA:
Bit0 : Reserved for synchronization error
Bit1-4 : 4 LSB OR result of 6 ODE error registers.
Bit5 : If any ODE data frame has a non-zero SYNC data consistency check bit, this bit is set.
Bit6 : If any ODE data frame has a non-zero SYNC Bunch Crossing count consistency check bit, this bit is set.
Bit7 : If any ODE data frame has a non-zero SYNC Event count consistency check bit, this bit is set.
Optical link no clock detect, 6-bit If no optical clock is received this bit is set,one bit per link.
Optical link disable, 6 bit Set if optical link is disabled via ECS, one bit per link.
Event size error, 6 bit Set if more (or less) than 35 words per event have beenreceived, one bit per link.
TLK link loss, 6 bit The TI TLK2502 indicates an error on reception; this bit is setif the link is not plugged, one bit per link.
Sync RAM full, 6 bitIndicates that an overflow occurred at the input sync RAM,one bit per link.
PP chip addr, 2 bit PP0="00",PP1="01", PP2="10", PP3="11".
ODEx Error, 12 bitError information of each ODE data frame (or optical link):
Bit 0-1: Overall hamming decode error ofthis ODE data frame.
Bit 2: BCN Mismatch. If BCNs decoded from ODE data frame and TTC are different, this bit is set.
Bit 3: EvID Mismatch. If EvIDs decoded from ODE data frame and TTC are different, this bit is set.
Bit 4: If this ODE data frame has a zero Bunch Crossing check bit, this bit is set.
Bit 5: If this ODE data frame has a non-zero SYNC data consistency check bit, this bit is set.
Bit 6: If this ODE data frame has a non-zero Header FIFO check bit, this bit is set.
Bit 7: If this ODE data frame has a non-zero SYNC Bunch Crossing count consistency check bit, this bit is set.
Bit 8: If this ODE data frame has a non-zero SYNC Event count consistency check bit, this bit is set.
Bit 9: If this ODE data frame has a non-zero error register, this bit is set.
Bit 10: ODE ID Mismatch. If ODE-ID from ODE data frame and ECS are different, this bit is set.
Bit 11: Checksum error.
5.MUON Received Data Format
The left part of the following picture shows the structure of an ODE Data Frame received viaOptical receive card. One PP-FPGA is connected to 6 optical links. So there are 6 ODE Data Frames for each PP-FPGA. An ODE Data Frame contains 35 words. However a zero word will be added at the beginning of the Data Frame at the RX part of PP-FPGA in order to be consistent with other sub-detectors. The total width of 6 ODE data frames in parallel is 32 times 6, which is bigger than the maximum width (128 bit) of the big RAM in PP-FPGA. For the purpose of buffering all 6 ODE data frames in parallel via one big RAM, the data are multiplexed on PP-FPGA in the format illustrated on the right part of the following picture. After being multiplexed, the data is 16-bit width and 72 half-word length, while the total width of 6 data frames is 16 times 6, which is less than 128.
Figure4: The format of ODE data frame and multiplex data.
6.Non zero-suppressed bank
The6 multiplex data of one PP-FPGA is distributed over 3 data sections as Fig.5.
Figure5: 3 data sections of non-zero suppressed data
The output format of the non-zero suppressed data is adapted to the FPGA design inorder to avoid intermediate data storage where ever possible. As a consequence, the data from 3 data sections are multiplexed again word by word as shown in Fig.6. The full 8-word “Event info” is added at the end for each PP-FPGA. Then SL-FPGA will receive 4 parts of non zero-suppressed data from 4 PP-FPGA and merge them together to make a complete non zero-suppressed bank as shown in the right part of Fig.6.
Figure6: The format of non zero-suppressed bank.
The size of the completenon-zero suppressed bank is fixed to 3592 byte (2x4 byte bank header + 4x4x224 bytenon-zero suppressed data)
7.Zero-suppressed bank
The format of zero-suppressed bank is shown in Fig.7. The first two words are bank header as describedin Fig.2. The third word is MUON specific header. The BCN is added in order to allow aminimum amount of synchronization check between different TELL1 boards.Then it is followed by PAD address field, which is very important and used for L1 trigger. The last data field is HIT address and data. The bank fields other than the common bank header will be discussed below.
Figure7: The format of zero-suppressed bank.
7.1. MUON specific header
PadCnt, 16 bit The total number of PADs in this bank. This numberallows to define the end of the PAD address field.
BCN, 8 bit Bunch counter
PP_ode_err, 8 bit It has the same format as the PP_ode_err defined in Fig.3. And it is the OR result of 4 PP_ode_err received from 4 PP-FPGAs except for bit 0 (Event error). The event error bit will be set by SL-FPGA in case that an error bank is generated due to synchronization problems. It indicates that aserious synchronization error has been detected.
7.2. PAD Address (For L1T)
Padx_Add, 16 bit The 16-bit address of each PAD. On one Tell1 board, each PAD has a unique address.
Padding,0 or 16 bit The PAD address field is padded with zeros if necessary in order to obtain 32-bit alignment.
7.3. HIT Address and Data
PPx Hit cnt, 16 bit The total number of HITs in PPx. It is also used to define the end of the HIT list of each PP-FPGA.
PPx Hit y, 16 bit It contains both the address and the data information for the corresponding HIT.
Bit 11-0: The 12-bit HIT address. On one Tell1 board, each HIT also has a unique address.
Bit 15-12: The 4-bit TDC value of this HIT.
Padding,0 or 16 bit The HIT address and Data field is also padded with zeros if necessary in order to obtain 32-bit alignment.
8.Error bank
The format of MUON Error bank is shown in Fig.8, which is similar with VELO and ST[3]. Please see the reference [3] to understand the definition of error bank. Error bank composes of 4 parts corresponding to 4 PP-FPGAs. Their definitions are identical.
Figure8: The format of error bank.
8.1. Fixed data field
The first two words: They are the first two words of “Event info”.
PAD length (Bytes), 16 bit: Length in byte of the TELL1 internal bank. It is defined twice.
HIT length (Bytes), 16 bit: Length in byte of the TELL1 internal bank.It is defined twice.
PADCnt, 16 bit: The total number of PAD on the corresponding PP-FPGA.
BCN, 8 bit: Bunch counter.
PP_ode_err, 8 bit:Its format is identical with the PP_ode_err defined in “Event info”.
Error bank length, 16 bit:Length of the error info in byte. If this field is set tozero, the PP-FPGA error info is not attached. Otherwise, it is set to 0x14 whichcorresponds to the length of 20 byte.
8.2.Optional data field
PP-FPGA info, 5 word:They are the 5 last words of “Eventinfo”.
Non-zero suppressed bank length,16 bit: Length in byte of the TELL1 internal bank.
Pedestal bank length,16 bit: Length in byte of the TELL1 internal bank.
References
[1]Guido Haefeli, Alex Gong, “Velo and ST non-zero suppressed bankdata format”, EDMS 692431.
[2]Guido Haefeli, Alex Gong, “ST zero suppressed bank data format”, EDMS 690583.
[3]Guido Haefeli, Alex Gong, “VELO and ST error bank data format”, EDMS 694818.
[4]B. Jost, N. Neufeld, “Raw-data transport format”, EDMS 499933.
[5]O. Callot, M. Cattaneo, R. Jacobsson, B. Jost, P. Mato, N. Neufeld, “Raw-dataFormat”, EDMS 565851.