Format
/Elements
/ TestCases /
All
Cases /Length
/Speed
/ LatePenalty /
TOTAL
/Words
/Cycles
98705710 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 54 / 40900751373 / 1 / 2 / 2 / 2 / 0 / 0 / waived / 7 / 74 / 630
00738718 / 1 / 2 / 2 / 1 / 0 / 0 / -1 / 5 / 55 / 469
00715452 / 1 / 1 / 1 / 1 / 0 / 0 / 4 / 67 / 714
99083482 / 1 / 2 / 2 / 2 / 0 / 0 / 7 / 85 / 686
00725052 / 1 / 2 / 2 / 2 / 0 / 0 / 7 / 85 / 685
98035294 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 69 / 677
95029278 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 55 / 551
99083247 / 1 / 2 / 0 / 1 / 0 / 0 / 4 / 64 / 453
99703733 / 1 / 2 / 2 / 1 / 1 / 0 / -1 / 6 / 48 / 421
00715399 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 65 / 676
00700365 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 51 / 431
00702184 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 60 / 572
00726039 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 53 / 432
00701181 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 67 / 564
00704534 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 57 / 513
00701122 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 66 / 495
00731954 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 51 / 442
00700349 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 59 / 543
00724906 / 1 / 2 / 1 / 1 / 0 / 0 / 5 / 64 / 539
00703419 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 52 / 437
00706134 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 54 / 488
00701763 / 1 / 2 / 2 / 1 / 1 / 1 / 8 / 47 / 364
00700947 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 62 / 477
00701544 / 1 / 2 / 2 / 1 / 0 / 1 / 7 / 52 / 382
00701878 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 66 / 498
00701827 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 59 / 461
98022127 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 68 / 679
99707670 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 62 / 456
00737264 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 64 / 494
00700824 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 65 / 495
00700162 / 1 / 2 / 1 / 2 / 0 / 0 / 6 / 52 / 431
00702029 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 59 / 461
00746558 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 53 / 457
00707241 / 2 / 2 / 2 / 1 / 1 / 1 / 9 / 42 / 379
00714054 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 74 / 857
00711929 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 58 / 546
00729301 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 53 / 415
00701499 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 59 / 551
99034592 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 73 / 664
00705369 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 62 / 506
00707866 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 56 / 437
00701149 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 53 / 457
00700832 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 52 / 456
00701608 / 1 / 1 / 0 / 1 / 0 / 0 / 3 / 51 / 453
00704577 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 55 / 492
00701894 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 65 / 482
00702328 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 64 / 474
00733482 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 87 / 686
00705318 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 61 / 458
00704593 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 57 / 400
00704905 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 58 / 434
00731049 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 57 / 433
00730468 / 2 / 2 / 2 / 1 / 0 / 1 / 8 / 55 / 382
00704753 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 56 / 410
00732252 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 60 / 454
95707665 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 54 / 451
00712761 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 69 / 677
99082965 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 62 / 678
00717562 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 63 / 490
00701157 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 61 / 460
00700592 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 53 / 496
00725212 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 59 / 484
00702571 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 60 / 460
00700306 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 53 / 403
00700621 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 58 / 496
00704673 / 2 / 2 / 2 / 2 / 1 / 0 / 9 / 45 / 436
00707487 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 62 / 539
00701886 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 58 / 441
00700816 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 55 / 420
00737213 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 67 / 564
01741898 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 61 / 536
00700576 / 2 / 2 / 2 / 1 / 1 / 0 / 8 / 48 / 455
00700402 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 57 / 463
00731145 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 73 / 452
00731153 / 2 / 2 / 2 / 1 / 0 / 0 / 7 / 57 / 433
00700429 / 1 / 2 / 2 / 1 / 0 / 0 / 6 / 60 / 416
00703734 / 1 / 2 / 0 / 1 / 0 / 0 / 4 / 60 / 999
Median Performance: 466 cycles; 59 words
20% improvement boundary (*0.83333): 386 cycles; 50 words
Mark Distribution:
Mark / Frequency
0 / 0
1 / 0
2 / 0
3 / 1
4 / 3
5 / 2
6 / 45
7 / 22
8 / 3
9 / 2
10 / 0
General Feedback:
- The late penalty was 1 mark per calendar day, unless a valid sick note/excuse was provided.
- It is not a good idea to use SFR’s to store variables. Some people used registers with addresses <0x20
- Please be careful which bits you check/set -- some persons used a bad arithmetic shift routine; others had trouble when xor’ing with the status register and accidentally changing banks in the process.
- While it may not always introduce a bug, it is a good idea to initialise the Carry flag to zero, if that is the initial value you need – there was no penalty if you didn’t.
- Booths algorithm does not work if 0x8000 is in the multiplicand. Some people presented test cases and the wrong result without explanation or comment.
- The performance test was 0x8000 in the multiplicand, and 0x5555 in the multiplier; chosen to determine a) if you’d caught (then modified test case 0x8001) or corrected for this case and b) to exercise the addition/subtraction as much as possible.
- Early exit on the zero cases – good idea!! But there were no extra marks, as I presumed it would not affect average performance by much – any protests?
- Very few people performed subtraction by taking the two’s complement of the number and then adding. Was this for performance reasons?
- Differentiating between directives and instructions: many people put instructions/directives in the wrong case, which I presume was due to being unable to distinguish between them. Quick hint: check the instruction set for the PIC … if it isn’t there then it’s a directive.
Sample answer:
LIST p=16F877
#include <p16F877.inc>
A_hiEQU 0x20
A_loEQU 0x21
Q_hi EQU 0x22
Q_lo EQU 0x23
M_hi EQU 0x24
M_lo EQU 0x25
nM_hiEQU 0x26
nM_loEQU 0x27
count EQU 0x28
storage EQU 0x29
ORG 0x00; initialization code
nop
goto Main
;
; subroutine tc16 replaces the 16 bit number stored
; HI:LO at the location specified by the FSR,
; with its two's complement.
; returns with carry flag set if there was an overflow
;
tc16comfINDF,F; complement hi byte
incfFSR ,F
comfINDF,F; complement lo byte
tc16incincfINDF,F; now the regular increment of lo byte
btfscSTATUS,Z
bsfSTATUS,C ; set the carry if we overflow
decfFSR, F
btfssSTATUS,C ; if no overflow then leave
return
incfszINDF,F; else increment hi byte
bcfSTATUS,C; clear flag if there was no overflow
return; all done
Mainmovlw0xB1; load up the numbers
movwfQ_hi
movlw 0x00
movwfQ_lo
movlw0x80
movwfM_hi
movwfnM_hi
movlw0x00
movwfM_lo
movwfnM_lo
movlw0x10
movwfcount
clrfSTATUS
movlwnM_hi; store the negative multiplier
movwfFSR
call tc16
clrfA_hi
clrfA_lo
clrfstorage
clrfSTATUS; clear out the flags
movfM_hi,W
xorwfQ_hi,W; store the result sign
movwfstorage
bthloopmovfQ_lo,W
andlw0x01
xorwfSTATUS,F; check the pair of bits
btfssSTATUS,C
gotoashft32
clrw
btfscQ_lo,0 ; if the Q_lo bit is 1 then subtract
addlw0x02
addlwM_lo
movwfFSR; load up FSR with M or -M
add16movfINDF,W; addition of M (or -M) to A
addwfA_lo,F
decfFSR ,F
movfINDF,W
btfscSTATUS,C
incfszA_hi,F
addwfA_hi,W
movwfA_hi
ashft32bcfSTATUS,C; 32 bit arithmetic shift for
btfscA_hi,7; A_hi,A_lo,M_hi,M_lo
bsfSTATUS,C
rrfA_hi,F
rrfA_lo,F
rrfQ_hi,F
rrfQ_lo,F
decfszcount,F; check if we are done
goto bthloop
; fudge for the 8000 case -- check if sign is correct.
movfA_hi,W
xorwfstorage,F
btfssstorage,7
goto done
movlwQ_hi
movwfFSR
calltc16
comfA_lo,F
comfA_hi,F
btfssSTATUS,C
goto done
incfszA_lo,F
bcfSTATUS,C
btfscSTATUS,C
incfszA_hi,F; note carry is not right
bcfSTATUS,C; at the end here!!
donesleep
END