Making Layout of CMOS Inverter
These steps are in the chapter 3 of the tutorial on the website:
It is easier to follow the steps from step 14 onwards if you have the tutorial open.
1.Move files: .simrc .cdsinit .cdsenv cds.lib .cshrc.ic into the folder cadence using the file manager. Click on View in the file manager. And select Show hidden objects to see the .* files. Drag and drop into folder named cadence. Also delete .libmgr and .libsel if present.
2.In console type source /usr/local/cadence/00setup.cdk. Enter. Type icfb &. Enter.
3. The library manager opens. It should look like the figure-6 in the tutorial.
4. Make new library (Layout). Click on File >New >Library. "Create library" window pops up.
5. Type Name: Layout and choose Attach to existing tech file .In the Technology Library area of the window.
6. Select AMI 1.6u ABN (2P,NPN). OK
7. You now have library Layout in your library manager.
8. Click on library Layout. And create a new cell view. File>New>Cellview.
9."Create a New File" window pops up. Write Cell Name: Inverter. Select Tool: Virtuoso.
10."Virtusos Layout Editing" window pops up. Click on Options; select Display Another window pops up. Select Defaults in that and hit Apply and then OK.
11.To make the layout of the inverter we need to get the layout of an nmos, a pmos.
To obtain the pmos click on Create and select Instance. (Or hit ‘i’ on the keyboard)
12."Create Instance " window pops up. Click on Browse.
13.Library Browser" window pops up. Select Library NCSU_TechLib_ami16
14.Select Cell pmos and place in the top right quadrant of the virtuoso layout editing window.
(For the time being we will continue with the default parameters. We will need to specify the parameters while doing the actual project.)
15. To check if the placement is correct we need to do the design rule check. To do that, click on verify. Select DRC. DRC stands for Design Rule Check.
Set the following options: Checking Method: flat ; Checking limit: full; Inclusion limit: 1000 ;
Rules file: divaDRC.rul; Rules Library:NCSU_TechLib_ami16.
OK. If there are any errors they will show up as white crosses on the component.
The most common error is that the component is not on the grid points. Moving the component around a little and placing it aligned on the dots on the screen, normally removes this error.
16.Create another instance in the same manner of nmos. Place it in the bottom right quadrant of the virtuoso layout editing window. Repeat step 15 to check for errors.
17. Create instance of ntap and place it to the left of the pmos, one edge touching. Repeat step 15 to check for errors.
18.Create instance of ptap and place it to the left of the nmos, one edge touching. Repeat step 15 to check for errors.
19. Create an instance m1_poly (which is a via between metal 1 and poly layers). Move around the various parts you have placed to make your layout look like the figure-58 in the tutorial. Repeat step 15 to check for errors.
20.You have a LSW window open which shows the various layers. Select metal 1-dg on that.
21. We will use this layer to connect the drains of the nmos and the pmos.
Create a rectangle and place it so as to cover the drains (blue & pink square on the right)
of both nmos and pmos. Figure-62. Repeat step 15 to check for errors.
22. To connect the gates together. Choose poly - dg in the LSW window.
23. Click on Create and select Rectangle. Draw a rectangle, which covers the gates (red rectangles) of both the nmos and pmos. Figure-63 in tutorial. Repeat step 15 to check for errors.
24.Connect this poly layer with the m1_poly via, by making another rectangle of poly, covering the central square of the via and touching the vertical poly layer connecting the 2 gates. Figure-64. Repeat step 15 to check for errors.
25. Now to make power and ground lines select metal1 on the LSW window.
26.Click on Create and select Polygon. Create a polygon covering the source of the pmos and the ntap.Figure-60 in the tutorial.
27.Create another polygon covering source of nmos and ptap. Figure-61 in the tutorial.
The layout should now look like the figure-65 in the tutorial.
28.Put pins by clicking on Create and selecting Pin. A window titled "Create Symbolic Pin" pops up. Give terminal names: VDD GND as inputoutput pins. Ensure that the pin type is metal1. Place on the upper and lower metal1 polygons respectively.
29.Create pin ‘IN’ in the same manner, with I/O type input. Place on the via m1_poly.
30.Create pin OUT with I/O type output and place on the metal layer connecting the drains of the pmos and the nmos.
31. Repeat step 15 to check for errors.
32.If there are no errors the icfb window will say that.
33.To extract the circuit. We need to have the inverter schematic under the same name in the same library. So make a cmos inverter, with the default nmos and pmos models. Using the tool Composer Schematic.
34. SO now when you click on the cell view inverter of the library. You should be able to see both the layout and schematic.
35. Go back to layout. Click on Verify and select extract. A window called “Extractor” pops up.
36.Click on Set Switches button. Another window called “Set Switches” pops up.
37. Select Extract_parasitic_caps and hit OK.
38. Back in the Extractor window the options should be:
Extract method: flat. Switchnames: Extract_parasitic_caps, Rules file: divaEXT.rul,
Rules Library:NCSU_TechLib_ami16
39. Click OK on the Extractor window.
40. If the Extraction is successful you can see the extracted circuit under the cell name inverter in the library manager.