Lesson 29Design of Registers in VHDL
Different Type of Registers
Registers are the internal storage units for any digital systems. They are of different sizes and are used for temporary storage of memory address(MAR), data to be written to main memory(write buffers), data to be read from memory (read buffers), status condition of an ALU (Flag/status register). In any case, registers are built using combination of flip-flops.
Registers are of different types
Serial-in-serial-out shift register
Serial-in-parallel-out shift register
Parallel-in-Serial-out shift register
parallel-in-parallel-out shift register
bidirectional shift register
- A simple 8-bit register in VHDL
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity register_8bit is
Port ( D : in STD_LOGIC_VECTOR(7 downto 0);
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(7 downto 0));
end register_8bit;
architecture Behavioral of register_8bit is
begin
process(CLK, D)
begin
if(CLK'event and CLK='1') then
Q<= D;
end if;
end process;
end Behavioral;
Registers also another input called “reset”. When the reset is active/or inactive the content of the registers are cleared else the register is loaded with the 8-bit content. The reset may be asynchronous or synchronous reset. The code below given bot the type of reset.
- Asynchronous reset: architecture Behavioral of register_8bit is
begin
process(CLK, D)
begin
if reset=’0’ then
Q <= “00000000”;
elsif (CLK'event and CLK='1') then
Q <= D;
end if;
end process;
end Behavioral;
- Synchronous reset
architecture Behavioral of register_8bit is
begin
process
begin
wait until CLK’event and CLK=’1’;
if (reset =’0’) then
Q <= “00000000”;
elsif (CLK'event and CLK='1') then
Q <= D;
end if;
end process;
end Behavioral;
Shift Registers
Shift registers are used to shift the contents of the register left or right by 1 bit. They are generally used for binary multiplication and division.
Shift Left Operation / Shift Right OperationQ(0) <= ‘0’
Q(1) <= Q(0);
--
-
Q(n-1) <= Q(n-2); / Q(0) <= Q(1);
Q(1)<= Q(2);
-
-
Q(n-1) <= ‘0’;
- Shift register using concurrent style of modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityshift_reg is
Port (
D: in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
endshift_reg;
architecture Behavioral of shift_reg is
signaltmp : std_logic_vector(3 downto 0);
begin
process(CLK,tmp, RESET)
begin
if RESET = '1' then
tmp<= "0000";
elsif (clk'event and clk='1') then
tmp(3) <= tmp(2);
tmp(2) <= tmp(1);
tmp(1) <= tmp(0);
tmp(0) <= D;
end if;
Q <= tmp;
end process;
end Behavioral;
- BehaviouralModlling of serial in serial out left shift register
entityshift_behave is
Port ( D: in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
endshift_behave;
architecture Behavioral of shift_behave is
signaltmp : std_logic_vector(3 downto 0):="0000";
begin
process(CLK,tmp, RESET)
begin
if RESET = '1' then
tmp<= "0000";
elsif (clk'event and clk='1') then
for I in 3 downto 1 LOOP
tmp(i) <= tmp(i-1);
end LOOP;
tmp(0)<= D;
end if;
Q <= tmp;
end process;
Questions:
Write VHDL program for shift right register ( or Serial-IN and serial-out shift register) in VHDL.
Write a VHDL program for serial-in and parallel out shift register
Write a VHDL program for parallel-in serial-out shift register.
Write a VHDL program for universal shift register