Lab 8: Agilent Ptolemy- PI4DQPSK Numeric Modulator
19
19 Lab 8: Agilent Ptolemy - PI4DQPSK Numeric Modulator
19 Lab 8: HP Ptolemy - PI4DQPSK Numeric Modulator 19-1
19.1 Objectives: 19-5
19.2 Numeric Modulator: 19-5
19.2.1 Numeric Data Source: 19-5
19.2.2 Encoding the Data: 19-7
19.2.3 View the Time Domain Iout Signal: 19-10
19.2.4 View the Constellation Diagram: 19-11
19.3 Tuning the symbol amplitude to +/-1 V: 19-12
19.3.1 Set up the tuning session: 19-12
19.3.2 Tuning process: 19-13
19.3.3 Tuning of variables: 19-14
19.4 Error Vector Measurement 19-15
19.5 Synthesize an FIR Filter: 19-17
19.5.1 DSP Filter Synthesis Tool: 19-17
19.5.2 Create an ADS Design of the Synthesized Filter: 19-19
19.5.3 Simulate with New “Synthesized Filter”: 19-20
19.6 Review of Lab 8 19-21
19.1 Objectives:
· Convert the PI4DQPSK modulator to a numeric DSP modulator design.
· Learn about the tuning procedure.
· Perform an EVM measurement to baseline the system performance.
· Design and synthesize an FIR filter to replace the built-in numeric raised cosine filter (optional).
19.2 Numeric Modulator:
19.2.1 Numeric Data Source:
1. Open the project named d:\users\ads\CommSys_Lab8_prj.
Refer to the pictures below and follow these steps to convert the timed PI4DQPSK modulator (last lab) to a numeric DSP design:
2. Open the schematic window and open the design “a_PI4DQPSK_Sys”.
3. Select “File> Save As...” and name it “b_PI4DQPSK_Sys_Numeric”.
4. Delete the “Data” source and “SymbolSplitter”.
5. Deactivate the rest of the system (everything to the right of the encoder, including the encoder).
6. Insert a “Bits” data source from the “Numeric Sources” library.
7. Place a “LogicToNRZ” element from the “Signal Converters” library and connect it to the output of the Bits data source.
This will convert the 0/1 logic output of the Bits data source to +/-1 V NRZ levels.
8. Place a “Distributor2” element from the “Numeric Control” library and connect it to the output of the “LogicToNRZ” converter.
This element has the same functionality as the SymbolSplitter timed element. The Distributor2 will take in two samples and place the first sample on the top output and the second sample on the lower output, essentially acting as a serial-to-parallel converter to form I and Q symbols from the serial input bits.
9. Place a TkPlot on the upper output of the Distributor2. Set the following parameters:
· Label to Q symbols
· Geometry to 500x400+0+0
· xTitle to Samples
· yTitle to Amplitude.
· XRange to 0 20
·
Persistence to 20
10.
Simulate and observe the results.
Note on the data bit shapes:
The data bits are not rectangular as they were when using the timed elements. This is because there is only one sample per symbol, which is acceptable for unfiltered symbols where the amplitude is either +1V or -1V with no ringing or overshoot. Having multiple samples per symbols adds no additional information when the symbol amplitudes are constant. However, this is not the case when the symbols have been distorted with Nyquist filters.
19.2.2 Encoding the Data:
1. Delete the TkPlot.
2. Re-activate the rest of the system.
3. Insert two “FloatToTimed” elements from the “Signal Converters” library. Connect them to the outputs of the “Distributor2” element. Set the parameter:
· TStep to Sym_time - units set to None
The numeric elements process samples, and have no timestep associated with them. “FloatToTimed” elements are being added to time stamp the samples. The TStep is set to Sym_time because each sample represents a symbol at one symbol time interval.
4. Connect the output of the “FloatToTimed” elements to the inputs of the “EncoderIQ”.
There is not a built-in PI4DQPSK encoder in the “Numeric” elements library, although one could be built using existing fundamental elements. The timed encoder will therefore be used and the timed signal will be converted back to float using the “TimedToFloat” element.
5.
Place two “TimedToFloat” elements from the Signal Converters library palette and connect them to the output of the EncoderIQ.
6. Refer to the following picture and insert two “RaisedCosine” filters from the “Numeric Communications” library. Set the following parameters:
· Interpolation to 10
· Length to 161
· SymbolInterval to 10
· ExcessBW to 0.35
· SquareRoot to Yes.
7. Connect each filter to the output of the “TimedToFloat” elements and delete the original timed filters.
8. Place two numeric “Gain” elements, from the “Numeric Math” library, and connect them to the output of the “RaisedCosine” filters. Set the parameter:
· Gain to 1
9. Place two “FloatToTimed” elements from the “Signal Converters” library and connect them to the output of the Gain elements. Set the
· TStep to Tstep - units set to None
10.
Connect the outputs of the “FloatToTimed” elements to the I and Q inputs of the “QAM_Mod”.
NOTES on the FIR Raised Cosine Filters:
· Interpolation: Since Nyquist filtering is now being applied to the baseband signals, it is necessary to have multiple samples per symbol since the symbol amplitudes will no longer be constant. The Tstep used in the timed PI4DQPSK modulator was set for 10 samples/symbol, so the interpolation factor for this filter is set to 10. This is the equivalent of upsampling the signal by 10 at the input of the filter.
·
Length: This filter is essentially a FIR filter that allows the number of taps to be specified. An odd number of taps results in a symmetrical impulse response for linear phase, with one tap coefficient lying in the center of the impulse. Thus, 80 taps lie to the right of the center and 80 to the left of the center for a filter with a Length of 161 (taps) as shown below. The delay through the filter is the distance from t=0 to the center of the impulse (t=0.329 mS in this example).
· SymbolInterval: This defines how many samples there are per symbol. In this exercise there are 10 samples/symbol. There is an 8 symbol delay (80 taps divided by 10 samples/symbol, where each tap represents a 1 sample delay) in this example, since there are 80 taps between t=0 and the center of the impulse response. This is equivalent to the 8*Sym_time delay used in the timed raised cosine filter, which equals 0.329 mS as seen above. Hence this filter is equivalent to the timed raised cosine filter used in the previous labs.
11. Simulate (the data set should default to “b_PI4DQPSK_Sys_Numeric”) and display the results.
19.2.3 View the Time Domain Iout Signal:
Display the demodulated I symbol stream, “Iout”. Observe the delay through the system and calculate the amount of time required to sample in the middle of the first symbol out of the system.
NOTE on symbol time:
The calculated start time, in terms of symbol time delays, is 17. This is due to an 8-symbol time delay through the timed raised cosine filter in the demodulator, plus the additional delay through the FIR filter. The actual start time for an IQ constellation measurement should be set to 19*Sym_time to allow 2 extra symbol times for the differential encoding.
Note the amplitude of the symbols is not +/-1 V. The gain parameter of the gain blocks G2 and G3 will be tuned such that the symbols (Iout and Qout) have amplitudes of +/-1 V. To make the tuning process easier we will plot the constellation diagram first.
19.2.4 View the Constellation Diagram:
1. Plot the constellation diagram:
The amplitude of the symbols is 0.4 V.
2. Save the data display window, with the name of “b_PI4DQPSK_Sys_Numeric”.
19.3 Tuning the symbol amplitude to +/-1 V:
19.3.1 Set up the tuning session:
Click on the Tune icon in schematic window:
This brings up the “Tune Control” window. This window is used to set up the parameters to be tuned and the range of values to be used for each parameter during tuning mode.
Move the cursor in the schematic window and note its crosshair format. The parameters to be tuned are selected by clicking on them in the schematic window. Select the gain of the two gain elements (G2 and G3) for this tuning procedure.
In the “Tune Control” window:
- click on the “Details” button;
- select the “After Pressing Tune” for the Simulate option.
The “Tune Control” window should appear as shown here.
In this window the user can change the Min / Max values, the nominal values and the step size individually for all parameters to be tuned. Both linear and logarithmic scales are supported.
19.3.2 Tuning process:
1. Change the value of G2 to 1.4 and then press “Tune”. Observe the constellation diagram in the DDS window.
2. Change the value of G3 to 1.6 and then press “Tune” and observe the effect of this change on the constellation diagram.
3.
Make a few more changes and note, on the constellation diagram, the effect of the balanced/unbalanced gain for the two paths, I and Q.
4. Find the values of G2 and G3 that make the symbol amplitudes equal to 1. The values obtained should be G2=G3=1.6.
5. Press “Reset” in the “Tune Control” window. This will bring the G2 and G3 to the original values of 1. Then press “Cancel” and “Yes” to accept losing the setup information. These operations cancel the tuning process and leave the schematic in the original form (before the tuning process was started).
19.3.3 Tuning of variables:
There is a method to ensure balanced gain during tuning. To do this, take the following steps:
1. Edit the variables block:
Add a variable named “Gain_value” with a value of 1.
2. Edit the G2 and G3 blocks:
Set the parameter:
· Gain to Gain_value
3. Start the tuning process by clicking on the “Tune” icon in “Schematic” window.
4. In the “Tune Control” window, change the “Simulate” option to “After pressing Tune”.
5. Select the “Gain_value” variable to be tuned, in the variables block.
6. In the “Tune Control” window, note the initial value of 1 for the “Gain_value” and press “Tune”. This will mark the starting point in the constellation diagram in the DDS window.
7.
Increase the value of “Gain_value”, in steps of 0.1, up to 1.6. The constellation diagram should look like the one bellow.
8. In the “Tune Control” window, press the “Update” button. This will update the schematic with the last value set during the tuning process.
9. Cancel the tuning procedure.
10. Save the schematic (the name should already be “b_PI4DQPSK_Sys_Numeric”).
19.4 Error Vector Measurement
Note: Because the EVM sink is a one port element it will be necessary to convert the two timed baseband outputs from the DQPSK_PI4Demod to a complex RF envelope in order to measure the EVM properly. We could just add a QAM modulator, but in this case we’ll add a RectToCx and a CxToTimed element to do the job because they don’t present a load to the Demodulator.
1. Insert a RectToCx element, from the Signal Converter palette or library, to the output of the new_DQPSK_PI4Demod element.
2. Add a CxToTimed element to the RectToCx element. Set the parameters Tstep=Tstep and Fcarrier=IF_freq.
3. Insert an “EVM” measurement from the “Sinks” library and connect it to the “CxToTimed” element output.
Set the following parameters:
· Start to 19*Sym_time - units set to None
· SymTime to Sym_time
· MeasType to EVM_RMS
· Symbol _Burst_Length to 64
· Modulation_Type to QPSK
·
OptimizeSamplingInstant to YES
4.
Re-simulate and display the EVM result in a list (table) format. The value is an RSS of the magnitude and phase error of each symbol measured. The value shown here represents a 0.4 % error.
5. Save the DDS window as “b_PI4DQPSK_Sys_Numeric”.
6. Close the DDS window.
NOTE on EVM:
The primary contributor to this error value is the modeling accuracy of the raised cosine filters. De-activating the raised cosine filters and bypassing them with a wire will confirm this. The delay value for the timed filters (or number of taps for the numeric filters) have a direct correlation to the modeling accuracy of the filter. Having a larger delay in the timed filters is equivalent to increasing the number of taps in the numeric filter, which results in a more accurate filter. A value of 0.4% is good baseline performance for this ideal system, since it is more than ten times better than the system specification of 12.5% error. The error introduced by the filters should be negligible with respect to the system impairments introduced by the final design.
19.5 Synthesize an FIR Filter:
19.5.1 DSP Filter Synthesis Tool:
Design and synthesize a FIR filter to replace the built-in numeric raised cosine filter.
1. Please close the existing Data Display windows before starting the DSP Filter Synthesis Tool.
2.
Select “Tools > DSP Filter > Start DSP Filter” to invoke Digital Filter Designer.
3. Set the following parameters:
· Filter Type to FIR
· Response Type to Root Raised Cosine
· Design Method to Windowing_Rectangular
· Auto Order to de-activated
· Order Number to 160
(to synthesize a filter with 161 taps: # of taps=order+1)
· Frequency Unit to kHz
· Sampling Frequency to 243 kHz
(10*symbol rate to correlate with the up-sampling factor of 10 used with the built-in numeric filter)
·
Symbol Rate to 24.3e3
· Roll Off to 0.35.
4. Click on the start icon to synthesize the filter.
5. Examine the filter performance in the DDS window that appears. The cutoff frequency of the filter should be approximately 12.15 kHz, or 1/2*Sym_time (this is only approximate because of the excess bandwidth factor of 0.35).
NOTE:
Place a marker on the center of the impulse response and notice that it correlates to 8* Sym_time, or 329.2 uS. This is the equivalent delay that was specified for the timed raised cosine filter in the previous lab. Increasing the delay for the timed raised cosine filters results in the impulse response being shifted to the right, which has a direct correlation to increasing the number of taps in a FIR filter. The performance of the filter improves with increasing delay in the timed filter and improves with increasing the number of taps in a FIR filter.