Issue Description:
My customer want to using OTSFA/OTSFB of AQSFRC to force PWM5A & PWM5B to low which followed with the PWM5A & PWM5B switch output operation, the wanted waveform of PWM5A&PWM5B shown as figure 1, but the tested waveform of PWM5A&PWM5B shown as figure 2, which from the test waveform, the forcing to low operation didn’t work as expected.
Figure 1: Wanted PWM5A&PWM5B for Forcing to Low operation
Figure 2 Tested waveform of PWM5A
CH1: Trigger Source CH4：PWM5A
Software Configuration & Operation:
The PWM5 Configuration in initialization shown as below:
void InitEPwm(void)
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
/***********************************************************************************************/
//Setup ePWM5
// Setup TBCLK
EPwm5Regs.TBPRD = INV_TB_PRD;//100M/8333=12kHz
// Setup counter mode
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;//Time-base Clock Prescale Bits 0x0/1 (default on reset) 0X1 /2 0X2 /4 0X3 /8 0X4 /16 0X5 /32 0X6 /64 0X7 /128
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//Counter Mode:0x0 Up-count mode, 0x1 Down-count mode,0x2 Up-down-count mode 0x3 Stop-freeze counter operation (default on reset)
EPwm5Regs.TBCTL.bit.FREE_SOFT =0x0; //Emulation Mode Bits. 00 Stop after the next time-base counter increment or decrement 01 Stop when counter completes a whole cycle:
EPwm5Regs.TBCTL.bit.HSPCLKDIV =TB_DIV1; //High Speed Time-base Clock Prescale Bits 0x0 /1 0x1 /2 (default on reset) 0x2 /4 0X3 /6 0X4 /8 0X5 /10 0X6 /12 0X7 /14
EPwm5Regs.TBCTL.bit.PHSDIR = TB_UP; //Phase Direction Bit. 0 Count down after the synchronization event. 1 Count up after the synchronization event.
EPwm5Regs.TBCTL.bit.PHSEN =TB_ENABLE;//Counter Register Load From Phase Register Enable:0 DISABLE 1 DISABLE
EPwm5Regs.TBCTL.bit.PRDLD =TB_SHADOW; //TB_IMMEDIATE; //Active Period Register Load From Shadow Register Select :0 use a shadow register,1 without using a shadow register
EPwm5Regs.TBCTL.bit.SWFSYNC =0;//Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated.
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //Synchronization Output Select 0x0 EPWMxSYNC ,0x1 CTR = zero ,0x2 CTR = CMPB,0x3 Disable EPWMxSYNCO signal
EPwm5Regs.TBPHS.bit.TBPHS = 0;//phase offset
EPwm5Regs.TBCTR = 0x0000;// Clear counter
// Set actions
EPwm5Regs.AQCTLA.bit.ZRO = AQ_SET;// Set PWM5A on zero
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;// Set PWM5A on event A, up count
EPwm5Regs.AQCTLB.bit.ZRO = AQ_SET;// Set PWM5B on zero
EPwm5Regs.AQCTLB.bit.CAU = AQ_CLEAR;
//EPwm5Regs.AQCTLB.bit.CBU = AQ_SET;
EPwm5Regs.AQSFRC.bit.RLDCSF = AQ_LD_ZERO_PRD;//AQ_LD_IMMEDIATE;2:load on counter equal to zero or period
EPwm5Regs.AQSFRC.bit.ACTSFA = AQ_ACTSF_LOW;
EPwm5Regs.AQSFRC.bit.ACTSFB = AQ_ACTSF_HI;
// Set Compare values
EPwm5Regs.CMPA.bit.CMPA = INV_TON_A_INIT;
EPwm5Regs.CMPB.bit.CMPB = INV_CMP_B;//15kHz欠频 //change the sync delay from 15 to 16 to assure the period capture
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB.
EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;//Active high complementary (AHC). EPWMxB is inverted.
EPwm5Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
EPwm5Regs.DBRED.bit.DBRED = INV_DB_RED;//150ns
EPwm5Regs.DBFED.bit.DBFED = INV_DB_FED;//1us
。。。。。。
EPwm5Regs.AQCSFRC.bit.CSFA = AQ_FORCE_LOW;
EPwm5Regs.AQCSFRC.bit.CSFB = AQ_FORCE_HI;
EDIS;
/***********************************************************************************************/
。。。。。
}
Using AQSFRC to force PWM5A/PWM5B output to low,
#define DRV_PWM_STOP_ONETIME {EPwm5Regs.AQSFRC.all = 0x00F5; }
Using HRCNFG to switch the PWM5A & PWM5B output.
#defineSWAPAB{EALLOW;EPwm5Regs.HRCNFG.all = 0x0080; EDIS;}
While the get the trigger signal, the software will force the PWM5A & PWM5B to low and will switch the PWM5A & PWM5B output while the switch condition triggered.
if(INV_PWM_A_ON_B_OFF == m_stInvCtrl.iPwmFlg)
{
DRV_PWMA_ON_PWMB_OFF;
InvCtrl_Int_PwmStopOnceAction();
BLANKING_ON;
}
voidInvCtrl_Int_PwmStopOnceAction(void)
{
if(m_stInvCtrl.iPwmStopOnceFlg == TRUE) //需要满足此条件，才封波一次
{
m_stInvCtrl.iPwmStopOnceFlg = FALSE;
DRV_PWM_STOP_ONETIME;//高频管发波停止
BLANKING_STOP_ONETIME;
}
if(PWM_SWAP_POS_POLE == m_stInvCtrl.iPwmSwapFlg)
{
SWAPAB;//5B对应高频上管，所以要发波转换
POLA_JUGE_LOW;//正半波极性判断信号置低
}
elseif(PWM_SWAP_NEG_POLE == m_stInvCtrl.iPwmSwapFlg)
{
NO_SWAPAB;//5A对应高频下管，所以要发波转换
POLA_JUGE_HIGH;//负半波极性判断信号置高
}
else
{}
}
The related #define shown as below:
#define DRV_PWM5A_ON {EPwm5Regs.AQCSFRC.bit.CSFA = 0;}
#define DRV_PWM5B_OFF {EPwm5Regs.AQCSFRC.bit.CSFB = 2;}
#define DRV_PWMA_ON_PWMB_OFF {DRV_PWM5A_ON;DRV_PWM5B_OFF; }
#define BLANKING_ON {EPwm6Regs.AQCSFRC.all = 0x0000; }
#define DRV_PWM_STOP_ONETIME {EPwm5Regs.AQSFRC.all = 0x00F5; }
#define BLANKING_STOP_ONETIME {EPwm6Regs.AQSFRC.bit.OTSFA = 0x1; }
#define NO_SWAPAB {EALLOW;EPwm5Regs.HRCNFG.all = 0x0000; EDIS;} //NO swap A and B/
#defineSWAPAB {EALLOW;EPwm5Regs.HRCNFG.all = 0x0080; EDIS;} //swap A and B
Support Need:
Could you kindly double check the software configuration and forcing to low operation logic?
Could you kindly give solutions for the PWM5A&PWM5B forcing to low operation and PWM5A&PWM5B switch operation?