Author, Author
Intrinsic Characteristics and Process Variation Effect of Nanoplate Vertical FET Devices
Minsoo Kim1, Kyul Ko1, Changbeom Woo 1, Myounggon Kang2, and Hyungcheol Shin1
1School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-747, Korea
2Department of Electronics Engineering, Korea National University of Transportation, Chungju 380-702, Korea
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How to cite this paper: Author 1, Author 2 and Author 3 (2016) Paper Title. ******, *, *-*.http://dx.doi.org/10.4236/***.2016.*****
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/ Abstract
In this paper, we have analyzed various characteristics of Vertical Field-Effect Transistor (VFET) with non-uniform channel structure using 3-D technology computer-aided design (TCAD) simulation. Due to Process Variation Effect (PVE), the thicknesses of the top channel (source) and the bottom channel (drain) are different [1]. Therefore, we compared average channel (6 nm) having different channel thickness with uniform 6 nm channel. For PVE case, source resistance becomes higher because the upper part is scaled down into 3.8 nm thickness. Therefore, driving current of PVE case is less than that of ideal case. In addition, the inversion charge in the top channel side is decreased in PVE case because of the quantum effect [2]. Therefore, intrinsic capacitance decreases in PVE case. RC delay increases in PVE case because the increasing rate of total resistance (14.6%) is larger than the decreasing rate of total capacitance (12.1%). Subthreshold swing (S.S) and drain-induced barrier lowering (DIBL) exhibit few differences between two cases, signifying that they have nearly same gate controllability. Thus, PVE degrades the intrinsic characteristics of the device with respect to two factors where one is driving current decrease (12.7%) induced by increase of source resistance and another is RC delay increase (0.74%) induced by the deficiency of inversion charge.
Keywords
Vertical FET (VFET), Process Variation Effect (PVE), Intrinsic characteristics.
Acknowledgements
This work was supported by the Brain Korea 21 Plus Project in 2016, Synopsys and Samsung Electronics.
References
[1] E, Baer., A, Burenkov., P, Evanschitzky. and J, Lorenz. (2016) Simulation of Process Variations in FinFET Transistor Patterning. Simulation of Semiconductor Processes and Devices 2016, 6-8 Sept. 2016, 209-302.
[2] Wu, Y.S. and Su, P. (2009) Analytical Quantum-Confinement Model for Short-Channel Gate-All-Around MOSFETs Under Subthreshold Region. IEEE Transactions on Electron Devices, 2 Oct. 2009, 2720-2725.
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