In This Project We Will Be Implementing a Low-Pass FIR Filter

ELEC 422

VLSI DESIGN

PROJECT PROPOSAL

Lerzan Celikkanat

Nathan Shaw

Xiengfeng Wang

In this project we will be implementing a low-pass FIR filter. The filter passes all frequencies up to 20 KHz. Starting at 20 KHz it attenuates up until 30 KHz. So set the Fpass to 20KHz which was a value given to us in the project specs. The Fstop value _in other words the frequencty value where it stops attenuating and doesn’t pass anything anymore_ was picked by us. We picked 30 KHz considering that we could get a reasonable accuracy with this much attenuation. However, we’re not sure if this “provides a sufficient amount of attenuation” as the spec sheet asks for. So we might have to change this Fstop value in the future.

We assigned it a sampling rate of 100 KHz, since this value is sufficiently larger than the sampling rate of an audio A/D (44 KHz). If we want it to operate noticably faster than the typical sampling rate of an audio A/D, we have to enter a value that is more than twice the 44 KHz value. So we picked 100 KHz.

We set the attenuation on the right side of the filter to 30dB where the pass-band ripple is set to 1dB. We tried a bunch of values and got various filter order calculations depending on this value. After having tried a few we settled on 30 dB.

We used the Xilinx FDA Tool to design the filter and see its response. When we entered the above values, the tool designed a filter with a minimum order of 11.

After observing the response of the filter we continued with the simulation steps:

The filter block was produced by the Xilinx FDA Tool, based on the design specs we entered.

When we apply a chirp signal to the filter, it gives a response as shown below. We can see in the spectrum graph that the signal passes the input completely, up until point of 20 KHz. After 20 KHz we can observe the attenuation which continues until 30 KHz.

In order to see a clearer wave, we played around with the display variables like number of samples and got the spectrum below. This one looks clearer and very similar to what we had in our first figure. This proives that the filter is working properly and is showing its characteristic behavior.

When we double click on the filter block that Xilinx designed for us we can view the following block diagram:

As far as hardware goes, we believe that we will need 11 8-bit adders, 14 8-bit multipliers, and 11 8x8-bit memory arrays.

We are unsure as to whether a filter of order 11 will fit in the time constraints that have been laid out. We’re concerned that an order 11 will take too long to process and might not fit within the 22 microseconds. The slowest block is the adder block and so we will need to measure the amount of time that one adder block takes between input to output. This should give us a good idea of what order our filter should be given the time constraint.

We observed our ripple adder that we made for our previous projects. In the irsim, the ripple adder adds about .88 ns to output the sum. However, irsim is not as accurate as Spice. So we have to run test the ripple adder in Spice, in order to come up with more accurate conclusion about how many adders we can use in this design.