ICS 331 Logic Design and Microprocessors Fall 2004
Lecture: MW 3:00-4:15pm, POST 126
Lab: R 4:30-5:45pm, Holmes 451
Instructor: Dr. Milica Barjaktarovic
Contact:
Office and phone:POST 314, x9097 – please do NOT leave messages
Office Hours:before and after the class: MW 10:30 – 11:30am, 1:15 – 2:30pm, 4:15 – 4:45pm.
Class web site:
TA:Jing Zhang
The purpose of this course is to gain understanding of logic and building computers from logic. We will apply this understanding to computer system architecture as well as various applications, such as networking. This course will also help with systematic planning, design, implementation and testing of efficient and accurate software.
Grading policy:
Homework5%
Quizzes25%
Midterm Exam25%
Final Exam25%
Lab20%
All assignments are due at the beginning of class. Homework is due one week after we cover the corresponding material in class. No late homework is accepted.
While attendance is not mandatory, we will have surprise quizzes (usually on homework topics).
Students are encouraged to do research and exchange ideas on the homework and programming assignments. However, each student is responsible to turn in his/her own work, and plagiarism will result in significant grade and/or academic penalty.
The students are required to work on labs in pairs. Each team member is expected to do original work.
Textbook:
Rob Williams, Computer Systems Architecture. Addison-Wesley, 2001.
WeekChapter Topic
8/231Introduction to hardware-software interface
8/252Binary and Hex Review
3Programming the 8085
8/317Programming the 8085
9/14Logic gates
No lab during the first two weeks of class.
No class on Monday Sep. 6, Labor Day
9/84Canonical circuits and Karnaugh maps
9/9Lab1Logic Gates
9/134Building computers from logic: the control unit
9/155Building computers from logic: the ALU
9/9Lab1Logic Gates (due)
9/206Building computers from logic: the memory
9/22
9/23Lab22-bit adder
9/277The Intel Pentium CPU
9/298Subroutines/debugging
9/30Lab22-bit adder (due)
10/49Serial Transmission
10/6s12Basic circuits
10/7Lab37-segment display
10/11Review
10/13MIDTERM EXAM
10/14Lab37-segment display (due)
10/18Review of the midterm exam
10/209Interrupt driven I/O
10/21Lab 4Using the oscilloscope
10/25s13Diodes, transistors
10/27s19555 Timer
10/28Lab 4Using the oscilloscope (due)
11/1s14Gates from transistors
11/3s15Flip-flops
11/4Lab5Constructing input and output ports
11/8s16Registers and counters
11/10s17Switches, memory, SAP
11/11Lab5Constructing input and output ports (due)
11/1514The memory hierarchy
11/1715The programmer’s viewpoint
11/18Lab 6Traffic lights using the 555 timer
11/2216LANs, WANs, WWW, Internet, and TCP/IP
11/2417Various access and other networks
11/25Lab 6Traffic lights using the 555 timer (due)
11/2919Intro to operating systems
12/121RISC processors
No lab during the last week of class.
12/6Review
12/8Last class. Review
TBDFINAL EXAM