Homework 5 – CSCE614 Computer Architecture

Spring 2016

1. (Virtual Memory) Consider a virtual memory system with the following properties:

- 17 bits virtual address

- 16 bits physical address

- The page offset field is 14 bits long.

(1)What is the page size? (5 pts)

(2)What is the page table size if one entry size is 4 bytes? (5 pts)

(3) The following is the page table for this machine. The first column indicates the valid bit. What is the physical address translation of virtual address “10000100000000001”? (5 pts)

1 / 00
0 / 01
0 / 11
1 / 10
1 / 11
0 / 00
0 / 10
1 / 01

(4) Assume that we have a 2-entry TLB. After referencing the following 4 memory

addresses (virtual addresses), what are the contents of the TLB? Assume that th

replacement policy is LRU. (Ignore the valid bit, dirty bit, reference bit) (20 pts)

11100010000000001

10011111011110000

11100000000000000

00011001000000001

2. (25 pts) (Cache Design) Suppose a 32-bit byte-addressable CPU accesses memory in the following order: 0x442B, 0x4419, 0x441B, 0x4428, 0x442B, 0x441E, 0x441F, 0x4423, 0x4433. Assume that we have 4 cache blocks. Initially the cache is empty. (1 word = 4 bytes)

a. (5 pts) If the cache is 2-way set associative with FIFO replacement policy, show the final contents of the cache with memory block number. Assume 1 block is 2 words. (Ignore the tag field and other bits.) What is the total number of misses? Show the number of bits of the Tag, Index, Block Offset fields.

b. (5 pts) If the cache is 2-way set associative with LRU replacement policy, show the final contents of the cache. Assume 1 block is 1 word. (Ignore the tag field and other bits.) What is the total number of misses?

c. (15 pts) If the cache is pseudo-associative, show the final contents of the cache with memory block number including rehash bits. Assume 1 block is 1 word. (Ignore the tag field and other bits.) What is the total number of misses?

3. (20 pts) Consider a 1GHz processor with single-level, split instruction and data caches. Both caches are write-through with write buffers (assuming write buffer does not stall and non-allocation for write miss), and have single-cycle hit time and 32-Byte blocks. Assuming there is no L2 cache. Main memory is interleaved, with 4 independent 8-Byte memory banks and a 50ns latency. The memory bus is 8 Bytes wide and has a clock frequency of ¼ of the processor frequency. The instruction cache miss rate is 0.1% and the data cache miss rate is 5% for loads, and 5% for stores. Assume 20% of the instructions are loads and 10% are stores. Determine:

a) (6 pts) The miss penalty.

b) (7 pts) The average memory access time.

c) (7 pts) The average number of bytes transferred on the bus (between memory and cache) for every 100 instructions executed. (Assuming every store write 32bit information)

Exercise questions from Textbook.

2.1, 2.8, 2.9, 5.1, 4.14